net/iavf: rework Tx path

[dpdk.git] / drivers / net / iavf / iavf_rxtx.h

diff --git a/drivers/net/iavf/iavf_rxtx.h b/drivers/net/iavf/iavf_rxtx.h
index 6d14290..863b381 100644 (file)
--- a/drivers/net/iavf/iavf_rxtx.h
+++ b/drivers/net/iavf/iavf_rxtx.h
@@ -403,6 +403,112 @@ enum iavf_rx_flex_desc_status_error_1_bits {
        IAVF_RX_FLEX_DESC_STATUS1_LAST /* this entry must be last!!! */
 };
 
+
+#define IAVF_TXD_DATA_QW1_DTYPE_SHIFT  (0)
+#define IAVF_TXD_DATA_QW1_DTYPE_MASK   (0xFUL << IAVF_TXD_QW1_DTYPE_SHIFT)
+
+#define IAVF_TXD_DATA_QW1_CMD_SHIFT    (4)
+#define IAVF_TXD_DATA_QW1_CMD_MASK     (0x3FFUL << IAVF_TXD_DATA_QW1_CMD_SHIFT)
+
+#define IAVF_TXD_DATA_QW1_OFFSET_SHIFT (16)
+#define IAVF_TXD_DATA_QW1_OFFSET_MASK  (0x3FFFFULL << \
+                                       IAVF_TXD_DATA_QW1_OFFSET_SHIFT)
+
+#define IAVF_TXD_DATA_QW1_OFFSET_MACLEN_SHIFT  (IAVF_TXD_DATA_QW1_OFFSET_SHIFT)
+#define IAVF_TXD_DATA_QW1_OFFSET_MACLEN_MASK   \
+       (0x7FUL << IAVF_TXD_DATA_QW1_OFFSET_MACLEN_SHIFT)
+
+#define IAVF_TXD_DATA_QW1_OFFSET_IPLEN_SHIFT   \
+       (IAVF_TXD_DATA_QW1_OFFSET_SHIFT + IAVF_TX_DESC_LENGTH_IPLEN_SHIFT)
+#define IAVF_TXD_DATA_QW1_OFFSET_IPLEN_MASK    \
+       (0x7FUL << IAVF_TXD_DATA_QW1_OFFSET_IPLEN_SHIFT)
+
+#define IAVF_TXD_DATA_QW1_OFFSET_L4LEN_SHIFT   \
+       (IAVF_TXD_DATA_QW1_OFFSET_SHIFT + IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
+#define IAVF_TXD_DATA_QW1_OFFSET_L4LEN_MASK    \
+       (0xFUL << IAVF_TXD_DATA_QW1_OFFSET_L4LEN_SHIFT)
+
+#define IAVF_TXD_DATA_QW1_MACLEN_MASK  \
+       (0x7FUL << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT)
+#define IAVF_TXD_DATA_QW1_IPLEN_MASK   \
+       (0x7FUL << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT)
+#define IAVF_TXD_DATA_QW1_L4LEN_MASK   \
+       (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
+#define IAVF_TXD_DATA_QW1_FCLEN_MASK   \
+       (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
+
+#define IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT      (34)
+#define IAVF_TXD_DATA_QW1_TX_BUF_SZ_MASK       \
+       (0x3FFFULL << IAVF_TXD_DATA_QW1_TX_BUF_SZ_SHIFT)
+
+#define IAVF_TXD_DATA_QW1_L2TAG1_SHIFT         (48)
+#define IAVF_TXD_DATA_QW1_L2TAG1_MASK          \
+       (0xFFFFULL << IAVF_TXD_DATA_QW1_L2TAG1_SHIFT)
+
+#define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_SHIFT  (11)
+#define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_MASK   \
+       (0x7UL << IAVF_TXD_CTX_QW1_IPSEC_PARAMS_CIPHERBLK_SHIFT)
+
+#define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_ICVLEN_SHIFT     (14)
+#define IAVF_TXD_CTX_QW1_IPSEC_PARAMS_ICVLEN_MASK      \
+       (0xFUL << IAVF_TXD_CTX_QW1_IPSEC_PARAMS_ICVLEN_SHIFT)
+
+#define IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_SHIFT         (30)
+#define IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_MASK          \
+       (0x3FFFFUL << IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_SHIFT)
+
+#define IAVF_TXD_CTX_QW1_TSYNC_PARAMS_TLEN_SHIFT       (30)
+#define IAVF_TXD_CTX_QW1_TSYNC_PARAMS_TLEN_MASK                \
+       (0x3FUL << IAVF_TXD_CTX_QW1_SEG_PARAMS_TLEN_SHIFT)
+
+#define IAVF_TXD_CTX_QW1_SEG_PARAMS_MSS_SHIFT          (50)
+#define IAVF_TXD_CTX_QW1_SEG_PARAMS_MSS_MASK           \
+       (0x3FFFUL << IAVF_TXD_CTX_QW1_SEG_PARAMS_MSS_SHIFT)
+
+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPT_SHIFT         (0)
+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPT_MASK          (0x3UL)
+
+enum iavf_tx_ctx_desc_tunnel_external_ip_type {
+       IAVF_TX_CTX_DESC_EIPT_NONE,
+       IAVF_TX_CTX_DESC_EIPT_IPV6,
+       IAVF_TX_CTX_DESC_EIPT_IPV4_NO_CHECKSUM_OFFLOAD,
+       IAVF_TX_CTX_DESC_EIPT_IPV4_CHECKSUM_OFFLOAD
+};
+
+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPLEN_SHIFT       (2)
+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIPLEN_MASK                (0x7FUL)
+
+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNT_SHIFT       (9)
+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNT_MASK                (0x3UL)
+
+enum iavf_tx_ctx_desc_tunnel_l4_tunnel_type {
+       IAVF_TX_CTX_DESC_L4_TUN_TYP_NO_UDP_GRE,
+       IAVF_TX_CTX_DESC_L4_TUN_TYP_UDP,
+       IAVF_TX_CTX_DESC_L4_TUN_TYP_GRE
+};
+
+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIP_NOINC_SHIFT    (11)
+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_EIP_NOINC_MASK     (0x1UL)
+
+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNLEN_SHIFT     (12)
+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4TUNLEN_MASK      (0x7FUL)
+
+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_DECTTL_SHIFT       (19)
+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_DECTTL_MASK                (0xFUL)
+
+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4T_CS_SHIFT       (23)
+#define IAVF_TXD_CTX_QW0_TUN_PARAMS_L4T_CS_MASK                (0x1UL)
+
+#define IAVF_TXD_CTX_QW0_L2TAG2_PARAM                  (32)
+#define IAVF_TXD_CTX_QW0_L2TAG2_MASK                   (0xFFFFUL)
+
+
+#define IAVF_RX_FLEX_DESC_IPSEC_CRYPTO_SAID_MASK       (0xFFFFF)
+
+/* for iavf_32b_rx_flex_desc.ptype_flex_flags0 member */
+#define IAVF_RX_FLEX_DESC_PTYPE_M      (0x3FF) /* 10-bits */
+
+
 /* for iavf_32b_rx_flex_desc.ptype_flex_flags0 member */
 #define IAVF_RX_FLEX_DESC_PTYPE_M      (0x3FF) /* 10-bits */
 
@@ -553,9 +659,10 @@ void iavf_dump_tx_descriptor(const struct iavf_tx_queue *txq,
        const volatile struct iavf_tx_desc *tx_desc = desc;
        enum iavf_tx_desc_dtype_value type;
 
-       type = (enum iavf_tx_desc_dtype_value)rte_le_to_cpu_64(
-               tx_desc->cmd_type_offset_bsz &
-               rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK));
+
+       type = (enum iavf_tx_desc_dtype_value)
+               rte_le_to_cpu_64(tx_desc->cmd_type_offset_bsz &
+                       rte_cpu_to_le_64(IAVF_TXD_DATA_QW1_DTYPE_MASK));
        switch (type) {
        case IAVF_TX_DESC_DTYPE_DATA:
                name = "Tx_data_desc";
@@ -569,8 +676,8 @@ void iavf_dump_tx_descriptor(const struct iavf_tx_queue *txq,
        }
 
        printf("Queue %d %s %d: QW0: 0x%016"PRIx64" QW1: 0x%016"PRIx64"\n",
-              txq->queue_id, name, tx_id, tx_desc->buffer_addr,
-              tx_desc->cmd_type_offset_bsz);
+               txq->queue_id, name, tx_id, tx_desc->buffer_addr,
+               tx_desc->cmd_type_offset_bsz);
 }
 
 #define FDIR_PROC_ENABLE_PER_QUEUE(ad, on) do { \