net/ice/base: add IP fragment flags

[dpdk.git] / drivers / net / ice / base / ice_adminq_cmd.h

diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index a31c27a..6b662b3 100644 (file)
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1513,6 +1513,7 @@ struct ice_aqc_get_link_status_data {
 #define ICE_AQ_LINK_TOPO_CRITICAL_SDP_ERR      BIT(4)
 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED   BIT(5)
 #define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE  BIT(6)
+#define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT      BIT(7)
        u8 link_info;
 #define ICE_AQ_LINK_UP                 BIT(0)  /* Link Status */
 #define ICE_AQ_LINK_FAULT              BIT(1)
@@ -1664,6 +1665,31 @@ struct ice_aqc_get_link_topo {
        u8 rsvd[9];
 };
 
+/* Read/Write I2C (direct, 0x06E2/0x06E3) */
+struct ice_aqc_i2c {
+       struct ice_aqc_link_topo_addr topo_addr;
+       __le16 i2c_addr;
+       u8 i2c_params;
+#define ICE_AQC_I2C_DATA_SIZE_S                0
+#define ICE_AQC_I2C_DATA_SIZE_M                (0xF << ICE_AQC_I2C_DATA_SIZE_S)
+#define ICE_AQC_I2C_ADDR_TYPE_M                BIT(4)
+#define ICE_AQC_I2C_ADDR_TYPE_7BIT     0
+#define ICE_AQC_I2C_ADDR_TYPE_10BIT    ICE_AQC_I2C_ADDR_TYPE_M
+#define ICE_AQC_I2C_DATA_OFFSET_S      5
+#define ICE_AQC_I2C_DATA_OFFSET_M      (0x3 << ICE_AQC_I2C_DATA_OFFSET_S)
+#define ICE_AQC_I2C_USE_REPEATED_START BIT(7)
+       u8 rsvd;
+       __le16 i2c_bus_addr;
+#define ICE_AQC_I2C_ADDR_7BIT_MASK     0x7F
+#define ICE_AQC_I2C_ADDR_10BIT_MASK    0x3FF
+       u8 i2c_data[4]; /* Used only by write command, reserved in read. */
+};
+
+/* Read I2C Response (direct, 0x06E2) */
+struct ice_aqc_read_i2c_resp {
+       u8 i2c_data[16];
+};
+
 /* Set Port Identification LED (direct, 0x06E9) */
 struct ice_aqc_set_port_id_led {
        u8 lport_num;
@@ -1675,6 +1701,16 @@ struct ice_aqc_set_port_id_led {
        u8 rsvd[13];
 };
 
+/* Set/Get GPIO (direct, 0x06EC/0x06ED) */
+struct ice_aqc_gpio {
+       __le16 gpio_ctrl_handle;
+#define ICE_AQC_GPIO_HANDLE_S  0
+#define ICE_AQC_GPIO_HANDLE_M  (0x3FF << ICE_AQC_GPIO_HANDLE_S)
+       u8 gpio_num;
+       u8 gpio_val;
+       u8 rsvd[12];
+};
+
 /* Read/Write SFF EEPROM command (indirect 0x06EE) */
 struct ice_aqc_sff_eeprom {
        u8 lport_num;
@@ -2837,6 +2873,9 @@ struct ice_aq_desc {
                struct ice_aqc_get_phy_caps get_phy;
                struct ice_aqc_set_phy_cfg set_phy;
                struct ice_aqc_restart_an restart_an;
+               struct ice_aqc_i2c read_write_i2c;
+               struct ice_aqc_read_i2c_resp read_i2c_resp;
+               struct ice_aqc_gpio read_write_gpio;
                struct ice_aqc_sff_eeprom read_write_sff_param;
                struct ice_aqc_set_port_id_led set_port_id_led;
                struct ice_aqc_get_sw_cfg get_sw_conf;
@@ -3073,6 +3112,8 @@ enum ice_adminq_opc {
        ice_aqc_opc_set_event_mask                      = 0x0613,
        ice_aqc_opc_set_mac_lb                          = 0x0620,
        ice_aqc_opc_get_link_topo                       = 0x06E0,
+       ice_aqc_opc_read_i2c                            = 0x06E2,
+       ice_aqc_opc_write_i2c                           = 0x06E3,
        ice_aqc_opc_set_port_id_led                     = 0x06E9,
        ice_aqc_opc_get_port_options                    = 0x06EA,
        ice_aqc_opc_set_port_option                     = 0x06EB,