net/ice/base: add AN masks to get PHY capabilities

[dpdk.git] / drivers / net / ice / base / ice_adminq_cmd.h

diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index 9a79c76..9375d61 100644 (file)
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1337,8 +1337,11 @@ struct ice_aqc_get_phy_caps_data {
 #define ICE_AQC_PHY_EN_LESM                            BIT(6)
 #define ICE_AQC_PHY_EN_AUTO_FEC                                BIT(7)
 #define ICE_AQC_PHY_CAPS_MASK                          MAKEMASK(0xff, 0)
-       u8 low_power_ctrl;
+       u8 low_power_ctrl_an;
 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG                BIT(0)
+#define ICE_AQC_PHY_AN_EN_CLAUSE28                     BIT(1)
+#define ICE_AQC_PHY_AN_EN_CLAUSE73                     BIT(2)
+#define ICE_AQC_PHY_AN_EN_CLAUSE37                     BIT(3)
        __le16 eee_cap;
 #define ICE_AQC_PHY_EEE_EN_100BASE_TX                  BIT(0)
 #define ICE_AQC_PHY_EEE_EN_1000BASE_T                  BIT(1)
@@ -1363,7 +1366,8 @@ struct ice_aqc_get_phy_caps_data {
 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN             BIT(6)
 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN             BIT(7)
 #define ICE_AQC_PHY_FEC_MASK                           MAKEMASK(0xdf, 0)
-       u8 rsvd1;       /* Byte 35 reserved */
+       u8 module_compliance_enforcement;
+#define ICE_AQC_MOD_ENFORCE_STRICT_MODE                        BIT(0)
        u8 extended_compliance_code;
 #define ICE_MODULE_TYPE_TOTAL_BYTE                     3
        u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
@@ -1412,11 +1416,11 @@ struct ice_aqc_set_phy_cfg_data {
 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT  BIT(5)
 #define ICE_AQ_PHY_ENA_LESM            BIT(6)
 #define ICE_AQ_PHY_ENA_AUTO_FEC                BIT(7)
-       u8 low_power_ctrl;
+       u8 low_power_ctrl_an;
        __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
        __le16 eeer_value;
        u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
-       u8 rsvd1;
+       u8 module_compliance_enforcement;
 };
 
 /* Set MAC Config command data structure (direct 0x0603) */
@@ -1720,6 +1724,32 @@ struct ice_aqc_nvm {
 #define ICE_AQC_NVM_LLDP_STATUS_M_LEN          4 /* In Bits */
 #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN         4 /* In Bytes */
 
+/* The result of netlist NVM read comes in a TLV format. The actual data
+ * (netlist header) starts from word offset 1 (byte 2). The FW strips
+ * out the type field from the TLV header so all the netlist fields
+ * should adjust their offset value by 1 word (2 bytes) in order to map
+ * their correct location.
+ */
+#define ICE_AQC_NVM_LINK_TOPO_NETLIST_MOD_ID           0x11B
+#define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN_OFFSET       1
+#define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN              2 /* In bytes */
+#define ICE_AQC_NVM_NETLIST_NODE_COUNT_OFFSET          2
+#define ICE_AQC_NVM_NETLIST_NODE_COUNT_LEN             2 /* In bytes */
+#define ICE_AQC_NVM_NETLIST_ID_BLK_START_OFFSET                5
+#define ICE_AQC_NVM_NETLIST_ID_BLK_LEN                 0x30 /* In words */
+
+/* netlist ID block field offsets (word offsets) */
+#define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_LOW       2
+#define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_HIGH      3
+#define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_LOW       4
+#define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_HIGH      5
+#define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_LOW            6
+#define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_HIGH           7
+#define ICE_AQC_NVM_NETLIST_ID_BLK_REV_LOW             8
+#define ICE_AQC_NVM_NETLIST_ID_BLK_REV_HIGH            9
+#define ICE_AQC_NVM_NETLIST_ID_BLK_SHA_HASH            0xA
+#define ICE_AQC_NVM_NETLIST_ID_BLK_CUST_VER            0x2F
+
 /* Used for 0x0704 as well as for 0x0705 commands */
 struct ice_aqc_nvm_cfg {
        u8      cmd_flags;
@@ -2154,6 +2184,20 @@ struct ice_aqc_get_pkg_info_resp {
        struct ice_aqc_get_pkg_info pkg_info[1];
 };
 
+/* Driver Shared Parameters (direct, 0x0C90) */
+struct ice_aqc_driver_shared_params {
+       u8 set_or_get_op;
+#define ICE_AQC_DRIVER_PARAM_OP_MASK           BIT(0)
+#define ICE_AQC_DRIVER_PARAM_SET               0
+#define ICE_AQC_DRIVER_PARAM_GET               1
+       u8 param_indx;
+#define ICE_AQC_DRIVER_PARAM_MAX_IDX           15
+       u8 rsvd[2];
+       __le32 param_val;
+       __le32 addr_high;
+       __le32 addr_low;
+};
+
 /* Lan Queue Overflow Event (direct, 0x1001) */
 struct ice_aqc_event_lan_overflow {
        __le32 prtdcb_ruptq;
@@ -2242,6 +2286,7 @@ struct ice_aq_desc {
                struct ice_aqc_get_vsi_resp get_vsi_resp;
                struct ice_aqc_download_pkg download_pkg;
                struct ice_aqc_get_pkg_info_list get_pkg_info_list;
+               struct ice_aqc_driver_shared_params drv_shared_params;
                struct ice_aqc_set_mac_lb set_mac_lb;
                struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
                struct ice_aqc_get_res_alloc get_res;
@@ -2464,6 +2509,8 @@ enum ice_adminq_opc {
        ice_aqc_opc_update_pkg                          = 0x0C42,
        ice_aqc_opc_get_pkg_info_list                   = 0x0C43,
 
+       ice_aqc_opc_driver_shared_params                = 0x0C90,
+
        /* Standalone Commands/Events */
        ice_aqc_opc_event_lan_overflow                  = 0x1001,
 };