net/ice/base: support flow director for GTPU with outer IPv6

[dpdk.git] / drivers / net / ice / base / ice_common.c

diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index 1d28a13..1683daf 100644 (file)
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -197,6 +197,10 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
        if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
                pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
                pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
+               ice_memcpy(pi->phy.link_info.module_type, &pcaps->module_type,
+                          sizeof(pi->phy.link_info.module_type),
+                          ICE_NONDMA_TO_NONDMA);
+
        }
 
        return status;
@@ -269,6 +273,18 @@ static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
                return ICE_MEDIA_UNKNOWN;
 
        if (hw_link_info->phy_type_low) {
+               /* 1G SGMII is a special case where some DA cable PHYs
+                * may show this as an option when it really shouldn't
+                * be since SGMII is meant to be between a MAC and a PHY
+                * in a backplane. Try to detect this case and handle it
+                */
+               if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII &&
+                   (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
+                   ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE ||
+                   hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
+                   ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE))
+                       return ICE_MEDIA_DA;
+
                switch (hw_link_info->phy_type_low) {
                case ICE_PHY_TYPE_LOW_1000BASE_SX:
                case ICE_PHY_TYPE_LOW_1000BASE_LX:
@@ -866,23 +882,23 @@ void ice_deinit_hw(struct ice_hw *hw)
  */
 enum ice_status ice_check_reset(struct ice_hw *hw)
 {
-       u32 cnt, reg = 0, grst_delay, uld_mask;
+       u32 cnt, reg = 0, grst_timeout, uld_mask;
 
        /* Poll for Device Active state in case a recent CORER, GLOBR,
         * or EMPR has occurred. The grst delay value is in 100ms units.
         * Add 1sec for outstanding AQ commands that can take a long time.
         */
-       grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
-                     GLGEN_RSTCTL_GRSTDEL_S) + 10;
+       grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
+                       GLGEN_RSTCTL_GRSTDEL_S) + 10;
 
-       for (cnt = 0; cnt < grst_delay; cnt++) {
+       for (cnt = 0; cnt < grst_timeout; cnt++) {
                ice_msec_delay(100, true);
                reg = rd32(hw, GLGEN_RSTAT);
                if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
                        break;
        }
 
-       if (cnt == grst_delay) {
+       if (cnt == grst_timeout) {
                ice_debug(hw, ICE_DBG_INIT,
                          "Global reset polling failed to complete.\n");
                return ICE_ERR_RESET_FAILED;
@@ -2038,40 +2054,21 @@ ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)
 {
        enum ice_status status;
        u32 cap_count;
-       u16 cbuf_len;
-       u8 retries;
-
-       /* The driver doesn't know how many capabilities the device will return
-        * so the buffer size required isn't known ahead of time. The driver
-        * starts with cbuf_len and if this turns out to be insufficient, the
-        * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs.
-        * The driver then allocates the buffer based on the count and retries
-        * the operation. So it follows that the retry count is 2.
-        */
-#define ICE_GET_CAP_BUF_COUNT  40
-#define ICE_GET_CAP_RETRY_COUNT        2
-
-       cap_count = ICE_GET_CAP_BUF_COUNT;
-       retries = ICE_GET_CAP_RETRY_COUNT;
+       void *cbuf;
 
-       do {
-               void *cbuf;
-
-               cbuf_len = (u16)(cap_count *
-                                sizeof(struct ice_aqc_list_caps_elem));
-               cbuf = ice_malloc(hw, cbuf_len);
-               if (!cbuf)
-                       return ICE_ERR_NO_MEMORY;
-
-               status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count,
-                                             opc, NULL);
-               ice_free(hw, cbuf);
+       cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN);
+       if (!cbuf)
+               return ICE_ERR_NO_MEMORY;
 
-               if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM)
-                       break;
+       /* Although the driver doesn't know the number of capabilities the
+        * device will return, we can simply send a 4KB buffer, the maximum
+        * possible size that firmware can return.
+        */
+       cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem);
 
-               /* If ENOMEM is returned, try again with bigger buffer */
-       } while (--retries);
+       status = ice_aq_discover_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count,
+                                     opc, NULL);
+       ice_free(hw, cbuf);
 
        return status;
 }
@@ -2474,10 +2471,6 @@ enum ice_status ice_update_link_info(struct ice_port_info *pi)
 
                status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
                                             pcaps, NULL);
-               if (status == ICE_SUCCESS)
-                       ice_memcpy(li->module_type, &pcaps->module_type,
-                                  sizeof(li->module_type),
-                                  ICE_NONDMA_TO_NONDMA);
 
                ice_free(hw, pcaps);
        }