/* Initialize max burst size */
if (!hw->max_burst_size)
ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
-
status = ice_init_fltr_mgmt_struct(hw);
if (status)
goto err_unroll_sched;
wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
- for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
+ /* Wait for the PFR to complete. The wait time is the global config lock
+ * timeout plus the PFR timeout which will account for a possible reset
+ * that is occurring during a download package operation.
+ */
+ for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT +
+ ICE_PF_RESET_WAIT_COUNT; cnt++) {
reg = rd32(hw, PFGEN_CTRL);
if (!(reg & PFGEN_CTRL_PFSWR_M))
break;
}
if (func_p) {
u32 reg_val, val;
+
if (hw->dcf_enabled)
break;
reg_val = rd32(hw, GLQF_FD_SIZE);
ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg);
- /* Configure the set phy data */
+ /* Configure the set PHY data */
status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode);
if (status) {
if (status != ICE_ERR_BAD_PTR)
if (status)
goto out;
+ cfg->caps |= (pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC);
+ cfg->link_fec_opt = pcaps->link_fec_options;
+
switch (fec) {
case ICE_FEC_BASER:
/* Clear RS bits, and AND BASE-R ability