return hw->mac_type == ICE_MAC_E810;
}
+/**
+ * ice_is_e810t
+ * @hw: pointer to the hardware structure
+ *
+ * returns true if the device is E810T based, false if not.
+ */
+bool ice_is_e810t(struct ice_hw *hw)
+{
+ return (hw->device_id == ICE_DEV_ID_E810C_SFP &&
+ hw->subsystem_device_id == ICE_SUBDEV_ID_E810T);
+}
+
/**
* ice_clear_pf_cfg - Clear PF configuration
* @hw: pointer to the hardware structure
if (status)
goto err_unroll_fltr_mgmt_struct;
+
+ /* enable jumbo frame support at MAC level */
+ status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);
+ if (status)
+ goto err_unroll_fltr_mgmt_struct;
+
/* Obtain counter base index which would be used by flow director */
status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
if (status)
ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
prefix, caps->max_mtu);
break;
+ case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE:
+ caps->pcie_reset_avoidance = (number > 0);
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: pcie_reset_avoidance = %d\n", prefix,
+ caps->pcie_reset_avoidance);
+ break;
+ case ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT:
+ caps->reset_restrict_support = (number == 1);
+ ice_debug(hw, ICE_DBG_INIT,
+ "%s: reset_restrict_support = %d\n", prefix,
+ caps->reset_restrict_support);
+ break;
case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0:
case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1:
case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2:
return ICE_SUCCESS;
}
+/**
+ * ice_aq_get_internal_data
+ * @hw: pointer to the hardware structure
+ * @cluster_id: specific cluster to dump
+ * @table_id: table ID within cluster
+ * @start: index of line in the block to read
+ * @buf: dump buffer
+ * @buf_size: dump buffer size
+ * @ret_buf_size: return buffer size (returned by FW)
+ * @ret_next_table: next block to read (returned by FW)
+ * @ret_next_index: next index to read (returned by FW)
+ * @cd: pointer to command details structure
+ *
+ * Get internal FW/HW data (0xFF08) for debug purposes.
+ */
+enum ice_status
+ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id,
+ u32 start, void *buf, u16 buf_size, u16 *ret_buf_size,
+ u16 *ret_next_table, u32 *ret_next_index,
+ struct ice_sq_cd *cd)
+{
+ struct ice_aqc_debug_dump_internals *cmd;
+ struct ice_aq_desc desc;
+ enum ice_status status;
+
+ cmd = &desc.params.debug_dump;
+
+ if (buf_size == 0 || !buf)
+ return ICE_ERR_PARAM;
+
+ ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_debug_dump_internals);
+
+ cmd->cluster_id = cluster_id;
+ cmd->table_id = CPU_TO_LE16(table_id);
+ cmd->idx = CPU_TO_LE32(start);
+
+ status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
+
+ if (!status) {
+ if (ret_buf_size)
+ *ret_buf_size = LE16_TO_CPU(desc.datalen);
+ if (ret_next_table)
+ *ret_next_table = LE16_TO_CPU(cmd->table_id);
+ if (ret_next_index)
+ *ret_next_index = LE32_TO_CPU(cmd->idx);
+ }
+
+ return status;
+}
+
/**
* ice_read_byte - read context byte into struct
* @src_ctx: the context structure to read from
*
* Initializes required config data for VSI, FD, ACL, and RSS before replay.
*/
-static enum ice_status
+enum ice_status
ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw)
{
enum ice_status status;