net/ice/base: add ethertype offset for QinQ dummy packet
[dpdk.git] / drivers / net / ice / base / ice_controlq.c
index 4c4f925..93f7bc0 100644 (file)
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2020 Intel Corporation
+ * Copyright(c) 2001-2021 Intel Corporation
  */
 
 #include "ice_common.h"
@@ -1110,6 +1110,7 @@ ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
                  struct ice_rq_event_info *e, u16 *pending)
 {
        u16 ntc = cq->rq.next_to_clean;
+       enum ice_aq_err rq_last_status;
        enum ice_status ret_code = ICE_SUCCESS;
        struct ice_aq_desc *desc;
        struct ice_dma_mem *bi;
@@ -1143,13 +1144,12 @@ ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
        desc = ICE_CTL_Q_DESC(cq->rq, ntc);
        desc_idx = ntc;
 
-       cq->rq_last_status = (enum ice_aq_err)LE16_TO_CPU(desc->retval);
+       rq_last_status = (enum ice_aq_err)LE16_TO_CPU(desc->retval);
        flags = LE16_TO_CPU(desc->flags);
        if (flags & ICE_AQ_FLAG_ERR) {
                ret_code = ICE_ERR_AQ_ERROR;
                ice_debug(hw, ICE_DBG_AQ_MSG, "Control Receive Queue Event 0x%04X received with error 0x%X\n",
-                         LE16_TO_CPU(desc->opcode),
-                         cq->rq_last_status);
+                         LE16_TO_CPU(desc->opcode), rq_last_status);
        }
        ice_memcpy(&e->desc, desc, sizeof(e->desc), ICE_DMA_TO_NONDMA);
        datalen = LE16_TO_CPU(desc->datalen);