net/mlx5: support more tunnel types

[dpdk.git] / drivers / net / ice / base / ice_controlq.h

diff --git a/drivers/net/ice/base/ice_controlq.h b/drivers/net/ice/base/ice_controlq.h
index 182db67..840fb5e 100644 (file)
--- a/drivers/net/ice/base/ice_controlq.h
+++ b/drivers/net/ice/base/ice_controlq.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2019
+ * Copyright(c) 2001-2021 Intel Corporation
  */
 
 #ifndef _ICE_CONTROLQ_H_
@@ -7,37 +7,41 @@
 
 #include "ice_adminq_cmd.h"
 
-
 /* Maximum buffer lengths for all control queue types */
 #define ICE_AQ_MAX_BUF_LEN 4096
 #define ICE_MBXQ_MAX_BUF_LEN 4096
+#define ICE_SBQ_MAX_BUF_LEN 512
 
 #define ICE_CTL_Q_DESC(R, i) \
        (&(((struct ice_aq_desc *)((R).desc_buf.va))[i]))
 
 #define ICE_CTL_Q_DESC_UNUSED(R) \
-       (u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
-             (R)->next_to_clean - (R)->next_to_use - 1)
+       ((u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
+              (R)->next_to_clean - (R)->next_to_use - 1))
 
 /* Defines that help manage the driver vs FW API checks.
  * Take a look at ice_aq_ver_check in ice_controlq.c for actual usage.
  */
 #define EXP_FW_API_VER_BRANCH          0x00
 #define EXP_FW_API_VER_MAJOR           0x01
-#define EXP_FW_API_VER_MINOR           0x03
+#define EXP_FW_API_VER_MINOR           0x05
 
 /* Different control queue types: These are mainly for SW consumption. */
 enum ice_ctl_q {
        ICE_CTL_Q_UNKNOWN = 0,
        ICE_CTL_Q_ADMIN,
        ICE_CTL_Q_MAILBOX,
+       ICE_CTL_Q_SB,
 };
 
-/* Control Queue default settings */
-#define ICE_CTL_Q_SQ_CMD_TIMEOUT       250  /* msecs */
+/* Control Queue timeout settings - max delay 1s */
+#define ICE_CTL_Q_SQ_CMD_TIMEOUT       10000 /* Count 10000 times */
+#define ICE_CTL_Q_SQ_CMD_USEC          100   /* Check every 100usec */
+#define ICE_CTL_Q_ADMIN_INIT_TIMEOUT   10    /* Count 10 times */
+#define ICE_CTL_Q_ADMIN_INIT_MSEC      100   /* Check every 100msec */
 
 struct ice_ctl_q_ring {
-       void *dma_head;                 /* Virtual address to dma head */
+       void *dma_head;                 /* Virtual address to DMA head */
        struct ice_dma_mem desc_buf;    /* descriptor ring memory */
        void *cmd_buf;                  /* command buffer memory */
 
@@ -60,6 +64,7 @@ struct ice_ctl_q_ring {
        u32 bal;
        u32 len_mask;
        u32 len_ena_mask;
+       u32 len_crit_mask;
        u32 head_mask;
 };
 
@@ -88,10 +93,9 @@ struct ice_ctl_q_info {
        u16 num_sq_entries;             /* send queue depth */
        u16 rq_buf_size;                /* receive queue buffer size */
        u16 sq_buf_size;                /* send queue buffer size */
+       enum ice_aq_err sq_last_status; /* last status on send queue */
        struct ice_lock sq_lock;                /* Send queue lock */
        struct ice_lock rq_lock;                /* Receive queue lock */
-       enum ice_aq_err sq_last_status; /* last status on send queue */
-       enum ice_aq_err rq_last_status; /* last status on receive queue */
 };
 
 #endif /* _ICE_CONTROLQ_H_ */