/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2019
+ * Copyright(c) 2001-2020 Intel Corporation
*/
#include "ice_common.h"
#define ICE_FDIR_NUM_PKT ARRAY_SIZE(ice_fdir_pkt)
-/* Flow Direcotr (FD) filter program descriptor Context */
-static const struct ice_ctx_ele ice_fd_fltr_desc_ctx_info[] = {
- /* Field Width LSB */
- ICE_CTX_STORE(ice_fd_fltr_desc_ctx, qindex, 11, 0),
- ICE_CTX_STORE(ice_fd_fltr_desc_ctx, comp_q, 1, 11),
- ICE_CTX_STORE(ice_fd_fltr_desc_ctx, comp_report, 2, 12),
- ICE_CTX_STORE(ice_fd_fltr_desc_ctx, fd_space, 2, 14),
- ICE_CTX_STORE(ice_fd_fltr_desc_ctx, cnt_index, 13, 16),
- ICE_CTX_STORE(ice_fd_fltr_desc_ctx, cnt_ena, 2, 29),
- ICE_CTX_STORE(ice_fd_fltr_desc_ctx, evict_ena, 1, 31),
- ICE_CTX_STORE(ice_fd_fltr_desc_ctx, toq, 3, 32),
- ICE_CTX_STORE(ice_fd_fltr_desc_ctx, toq_prio, 3, 35),
- ICE_CTX_STORE(ice_fd_fltr_desc_ctx, dpu_recipe, 2, 38),
- ICE_CTX_STORE(ice_fd_fltr_desc_ctx, drop, 1, 40),
- ICE_CTX_STORE(ice_fd_fltr_desc_ctx, flex_prio, 3, 41),
- ICE_CTX_STORE(ice_fd_fltr_desc_ctx, flex_mdid, 4, 44),
- ICE_CTX_STORE(ice_fd_fltr_desc_ctx, flex_val, 16, 48),
- ICE_CTX_STORE(ice_fd_fltr_desc_ctx, dtype, 4, 64),
- ICE_CTX_STORE(ice_fd_fltr_desc_ctx, pcmd, 1, 68),
- ICE_CTX_STORE(ice_fd_fltr_desc_ctx, desc_prof_prio, 3, 69),
- ICE_CTX_STORE(ice_fd_fltr_desc_ctx, desc_prof, 6, 72),
- ICE_CTX_STORE(ice_fd_fltr_desc_ctx, fd_vsi, 10, 78),
- ICE_CTX_STORE(ice_fd_fltr_desc_ctx, swap, 1, 88),
- ICE_CTX_STORE(ice_fd_fltr_desc_ctx, fdid_prio, 3, 89),
- ICE_CTX_STORE(ice_fd_fltr_desc_ctx, fdid_mdid, 4, 92),
- ICE_CTX_STORE(ice_fd_fltr_desc_ctx, fdid, 32, 96),
- { 0 }
-};
-
/**
* ice_set_dflt_val_fd_desc
* @fd_fltr_ctx: pointer to fd filter descriptor
fd_fltr_ctx->fdid = ICE_FXD_FLTR_QW1_FDID_ZERO;
}
+/**
+ * ice_set_fd_desc_val
+ * @ctx: pointer to fd filter descriptor context
+ * @fdir_desc: populated with fd filter descriptor values
+ */
+static void
+ice_set_fd_desc_val(struct ice_fd_fltr_desc_ctx *ctx,
+ struct ice_fltr_desc *fdir_desc)
+{
+ u64 qword;
+
+ /* prep QW0 of FD filter programming desc */
+ qword = ((u64)ctx->qindex << ICE_FXD_FLTR_QW0_QINDEX_S) &
+ ICE_FXD_FLTR_QW0_QINDEX_M;
+ qword |= ((u64)ctx->comp_q << ICE_FXD_FLTR_QW0_COMP_Q_S) &
+ ICE_FXD_FLTR_QW0_COMP_Q_M;
+ qword |= ((u64)ctx->comp_report << ICE_FXD_FLTR_QW0_COMP_REPORT_S) &
+ ICE_FXD_FLTR_QW0_COMP_REPORT_M;
+ qword |= ((u64)ctx->fd_space << ICE_FXD_FLTR_QW0_FD_SPACE_S) &
+ ICE_FXD_FLTR_QW0_FD_SPACE_M;
+ qword |= ((u64)ctx->cnt_index << ICE_FXD_FLTR_QW0_STAT_CNT_S) &
+ ICE_FXD_FLTR_QW0_STAT_CNT_M;
+ qword |= ((u64)ctx->cnt_ena << ICE_FXD_FLTR_QW0_STAT_ENA_S) &
+ ICE_FXD_FLTR_QW0_STAT_ENA_M;
+ qword |= ((u64)ctx->evict_ena << ICE_FXD_FLTR_QW0_EVICT_ENA_S) &
+ ICE_FXD_FLTR_QW0_EVICT_ENA_M;
+ qword |= ((u64)ctx->toq << ICE_FXD_FLTR_QW0_TO_Q_S) &
+ ICE_FXD_FLTR_QW0_TO_Q_M;
+ qword |= ((u64)ctx->toq_prio << ICE_FXD_FLTR_QW0_TO_Q_PRI_S) &
+ ICE_FXD_FLTR_QW0_TO_Q_PRI_M;
+ qword |= ((u64)ctx->dpu_recipe << ICE_FXD_FLTR_QW0_DPU_RECIPE_S) &
+ ICE_FXD_FLTR_QW0_DPU_RECIPE_M;
+ qword |= ((u64)ctx->drop << ICE_FXD_FLTR_QW0_DROP_S) &
+ ICE_FXD_FLTR_QW0_DROP_M;
+ qword |= ((u64)ctx->flex_prio << ICE_FXD_FLTR_QW0_FLEX_PRI_S) &
+ ICE_FXD_FLTR_QW0_FLEX_PRI_M;
+ qword |= ((u64)ctx->flex_mdid << ICE_FXD_FLTR_QW0_FLEX_MDID_S) &
+ ICE_FXD_FLTR_QW0_FLEX_MDID_M;
+ qword |= ((u64)ctx->flex_val << ICE_FXD_FLTR_QW0_FLEX_VAL_S) &
+ ICE_FXD_FLTR_QW0_FLEX_VAL_M;
+ fdir_desc->qidx_compq_space_stat = CPU_TO_LE64(qword);
+
+ /* prep QW1 of FD filter programming desc */
+ qword = ((u64)ctx->dtype << ICE_FXD_FLTR_QW1_DTYPE_S) &
+ ICE_FXD_FLTR_QW1_DTYPE_M;
+ qword |= ((u64)ctx->pcmd << ICE_FXD_FLTR_QW1_PCMD_S) &
+ ICE_FXD_FLTR_QW1_PCMD_M;
+ qword |= ((u64)ctx->desc_prof_prio << ICE_FXD_FLTR_QW1_PROF_PRI_S) &
+ ICE_FXD_FLTR_QW1_PROF_PRI_M;
+ qword |= ((u64)ctx->desc_prof << ICE_FXD_FLTR_QW1_PROF_S) &
+ ICE_FXD_FLTR_QW1_PROF_M;
+ qword |= ((u64)ctx->fd_vsi << ICE_FXD_FLTR_QW1_FD_VSI_S) &
+ ICE_FXD_FLTR_QW1_FD_VSI_M;
+ qword |= ((u64)ctx->swap << ICE_FXD_FLTR_QW1_SWAP_S) &
+ ICE_FXD_FLTR_QW1_SWAP_M;
+ qword |= ((u64)ctx->fdid_prio << ICE_FXD_FLTR_QW1_FDID_PRI_S) &
+ ICE_FXD_FLTR_QW1_FDID_PRI_M;
+ qword |= ((u64)ctx->fdid_mdid << ICE_FXD_FLTR_QW1_FDID_MDID_S) &
+ ICE_FXD_FLTR_QW1_FDID_MDID_M;
+ qword |= ((u64)ctx->fdid << ICE_FXD_FLTR_QW1_FDID_S) &
+ ICE_FXD_FLTR_QW1_FDID_M;
+ fdir_desc->dtype_cmd_vsi_fdid = CPU_TO_LE64(qword);
+}
+
/**
* ice_fdir_get_prgm_desc - set a fdir descriptor from a fdir filter struct
* @hw: pointer to the hardware structure
if (input->dest_ctl == ICE_FLTR_PRGM_DESC_DEST_DROP_PKT) {
fdir_fltr_ctx.drop = ICE_FXD_FLTR_QW0_DROP_YES;
fdir_fltr_ctx.qindex = 0;
+ } else if (input->dest_ctl ==
+ ICE_FLTR_PRGM_DESC_DEST_DIRECT_PKT_OTHER) {
+ fdir_fltr_ctx.drop = ICE_FXD_FLTR_QW0_DROP_NO;
+ fdir_fltr_ctx.qindex = 0;
} else {
if (input->dest_ctl ==
ICE_FLTR_PRGM_DESC_DEST_DIRECT_PKT_QGROUP)
fdir_fltr_ctx.cnt_index = input->cnt_index;
fdir_fltr_ctx.fd_vsi = ice_get_hw_vsi_num(hw, input->dest_vsi);
fdir_fltr_ctx.evict_ena = ICE_FXD_FLTR_QW0_EVICT_ENA_FALSE;
- fdir_fltr_ctx.toq_prio = 3;
+ if (input->dest_ctl == ICE_FLTR_PRGM_DESC_DEST_DIRECT_PKT_OTHER)
+ fdir_fltr_ctx.toq_prio = 0;
+ else
+ fdir_fltr_ctx.toq_prio = 3;
fdir_fltr_ctx.pcmd = (add) ? ICE_FXD_FLTR_QW1_PCMD_ADD :
ICE_FXD_FLTR_QW1_PCMD_REMOVE;
fdir_fltr_ctx.swap = ICE_FXD_FLTR_QW1_SWAP_NOT_SET;
fdir_fltr_ctx.comp_q = ICE_FXD_FLTR_QW0_COMP_Q_ZERO;
fdir_fltr_ctx.comp_report = ICE_FXD_FLTR_QW0_COMP_REPORT_SW;
- fdir_fltr_ctx.fdid_prio = 3;
+ fdir_fltr_ctx.fdid_prio = input->fdid_prio;
fdir_fltr_ctx.desc_prof = 1;
fdir_fltr_ctx.desc_prof_prio = 3;
ice_set_fd_desc_val(&fdir_fltr_ctx, fdesc);
}
-/**
- * ice_set_fd_desc_val
- * @fd_fltr_ctx: pointer to fd filter descriptor context
- * @fdir_desc: populated with fd filter descriptor values
- */
-void
-ice_set_fd_desc_val(struct ice_fd_fltr_desc_ctx *fd_fltr_ctx,
- struct ice_fltr_desc *fdir_desc)
-{
- u64 ctx_buf[2] = { 0 };
-
- ice_set_ctx((u8 *)fd_fltr_ctx, (u8 *)ctx_buf,
- ice_fd_fltr_desc_ctx_info);
- fdir_desc->qidx_compq_space_stat = CPU_TO_LE64(ctx_buf[0]);
- fdir_desc->dtype_cmd_vsi_fdid = CPU_TO_LE64(ctx_buf[1]);
-}
-
/**
* ice_alloc_fd_res_cntr - obtain counter resource for FD type
* @hw: pointer to the hardware structure
*/
int ice_get_fdir_cnt_all(struct ice_hw *hw)
{
- return hw->func_caps.fd_fltr_guar +
- hw->func_caps.fd_fltr_best_effort;
+ return hw->func_caps.fd_fltr_guar + hw->func_caps.fd_fltr_best_effort;
}
/**
}
/**
- * ice_pkt_insert_u8_tc - insert a u8 value into a memory buffer for tc ipv6.
+ * ice_pkt_insert_u8_tc - insert a u8 value into a memory buffer for TC ipv6.
* @pkt: packet buffer
* @offset: offset into buffer
* @data: 8 bit value to convert and insert into pkt at offset
*
- * This function is designed for inserting Traffic Class (tc) for IPv6,
- * since that tc is not aligned in number of bytes. Here we split it out
+ * This function is designed for inserting Traffic Class (TC) for IPv6,
+ * since that TC is not aligned in number of bytes. Here we split it out
* into two part and fill each byte with data copy from pkt, then insert
* the two bytes data one by one.
*/
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP:
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP:
case ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER:
+ ice_pkt_insert_u32(loc, ICE_IPV4_SRC_ADDR_OFFSET,
+ input->ip.v4.src_ip);
+ ice_pkt_insert_u32(loc, ICE_IPV4_DST_ADDR_OFFSET,
+ input->ip.v4.dst_ip);
+ ice_pkt_insert_u32(loc, ICE_IPV4_GTPU_TEID_OFFSET,
+ input->gtpu_data.teid);
ice_pkt_insert_u6_qfi(loc, ICE_IPV4_GTPU_QFI_OFFSET,
input->gtpu_data.qfi);
break;
struct ice_fdir_fltr *
ice_fdir_find_fltr_by_idx(struct ice_hw *hw, u32 fltr_idx)
{
- struct ice_fdir_fltr *rule = NULL;
+ struct ice_fdir_fltr *rule;
LIST_FOR_EACH_ENTRY(rule, &hw->fdir_list_head, ice_fdir_fltr,
fltr_node) {
* ice_fdir_update_cntrs - increment / decrement filter counter
* @hw: pointer to hardware structure
* @flow: filter flow type
+ * @acl_fltr: true indicates an ACL filter
* @add: true implies filters added
*/
void
-ice_fdir_update_cntrs(struct ice_hw *hw, enum ice_fltr_ptype flow, bool add)
+ice_fdir_update_cntrs(struct ice_hw *hw, enum ice_fltr_ptype flow,
+ bool acl_fltr, bool add)
{
int incr;
- incr = (add) ? 1 : -1;
+ incr = add ? 1 : -1;
hw->fdir_active_fltr += incr;
- if (flow == ICE_FLTR_PTYPE_NONF_NONE || flow >= ICE_FLTR_PTYPE_MAX)
+ if (flow == ICE_FLTR_PTYPE_NONF_NONE || flow >= ICE_FLTR_PTYPE_MAX) {
ice_debug(hw, ICE_DBG_SW, "Unknown filter type %d\n", flow);
- else
- hw->fdir_fltr_cnt[flow] += incr;
+ } else {
+ if (acl_fltr)
+ hw->acl_fltr_cnt[flow] += incr;
+ else
+ hw->fdir_fltr_cnt[flow] += incr;
+ }
}
/**
}
/**
- * ice_fdir_comp_ipv6_rules - compare 2 filters
+ * ice_fdir_comp_rules - compare 2 filters
* @a: a Flow Director filter data structure
* @b: a Flow Director filter data structure
* @v6: bool true if v6 filter
*/
bool ice_fdir_is_dup_fltr(struct ice_hw *hw, struct ice_fdir_fltr *input)
{
- enum ice_fltr_ptype flow_type;
struct ice_fdir_fltr *rule;
bool ret = false;
- rule = NULL;
-
LIST_FOR_EACH_ENTRY(rule, &hw->fdir_list_head, ice_fdir_fltr,
fltr_node) {
- if (rule->flow_type == input->flow_type) {
- flow_type = input->flow_type;
- if (flow_type == ICE_FLTR_PTYPE_NONF_IPV4_TCP ||
- flow_type == ICE_FLTR_PTYPE_NONF_IPV4_UDP ||
- flow_type == ICE_FLTR_PTYPE_NONF_IPV4_SCTP ||
- flow_type == ICE_FLTR_PTYPE_NONF_IPV4_OTHER)
- ret = ice_fdir_comp_rules(rule, input, false);
+ enum ice_fltr_ptype flow_type;
+
+ if (rule->flow_type != input->flow_type)
+ continue;
+
+ flow_type = input->flow_type;
+ if (flow_type == ICE_FLTR_PTYPE_NONF_IPV4_TCP ||
+ flow_type == ICE_FLTR_PTYPE_NONF_IPV4_UDP ||
+ flow_type == ICE_FLTR_PTYPE_NONF_IPV4_SCTP ||
+ flow_type == ICE_FLTR_PTYPE_NONF_IPV4_OTHER)
+ ret = ice_fdir_comp_rules(rule, input, false);
+ else
+ ret = ice_fdir_comp_rules(rule, input, true);
+ if (ret) {
+ if (rule->fltr_id == input->fltr_id &&
+ rule->q_index != input->q_index)
+ ret = false;
else
- ret = ice_fdir_comp_rules(rule, input, true);
- if (ret) {
- if (rule->fltr_id == input->fltr_id &&
- rule->q_index != input->q_index)
- ret = false;
- else
- break;
- }
+ break;
}
}
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