/* ICE_FLOW_FIELD_IDX_GTPU_UP_TEID */
ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_GTPU_UP, 12,
ICE_FLOW_FLD_SZ_GTP_TEID),
+ /* ICE_FLOW_FIELD_IDX_GTPU_UP_QFI */
+ ICE_FLOW_FLD_INFO_MSK(ICE_FLOW_SEG_HDR_GTPU_UP, 22,
+ ICE_FLOW_FLD_SZ_GTP_QFI, 0x3f00),
/* ICE_FLOW_FIELD_IDX_GTPU_DWN_TEID */
ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_GTPU_DWN, 12,
ICE_FLOW_FLD_SZ_GTP_TEID),
+ /* ICE_FLOW_FIELD_IDX_GTPU_DWN_QFI */
+ ICE_FLOW_FLD_INFO_MSK(ICE_FLOW_SEG_HDR_GTPU_DWN, 22,
+ ICE_FLOW_FLD_SZ_GTP_QFI, 0x3f00),
/* PPPOE */
/* ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID */
ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_PPPOE, 2,
u16 sib_mask = 0;
u16 mask;
u16 off;
+ bool exist;
flds = params->prof->segs[seg].fields;
break;
case ICE_FLOW_FIELD_IDX_IPV6_TTL:
case ICE_FLOW_FIELD_IDX_IPV6_PROT:
- prot_id = seg == 0 ? ICE_PROT_IPV6_OF_OR_S : ICE_PROT_IPV6_IL;
+ prot_id = ICE_PROT_IPV6_NEXT_PROTO;
+ exist = ice_check_ddp_support_proto_id(hw, prot_id);
+ if (!exist)
+ prot_id = seg == 0 ?
+ ICE_PROT_IPV6_OF_OR_S :
+ ICE_PROT_IPV6_IL;
+ else
+ prot_id = seg == 0 ?
+ ICE_PROT_IPV6_NEXT_PROTO :
+ ICE_PROT_IPV6_IL;
/* TTL and PROT share the same extraction seq. entry.
* Each is considered a sibling to the other in terms of sharing
case ICE_FLOW_FIELD_IDX_GTPU_DWN_TEID:
case ICE_FLOW_FIELD_IDX_GTPU_EH_TEID:
case ICE_FLOW_FIELD_IDX_GTPU_EH_QFI:
+ case ICE_FLOW_FIELD_IDX_GTPU_UP_QFI:
+ case ICE_FLOW_FIELD_IDX_GTPU_DWN_QFI:
/* GTP is accessed through UDP OF protocol */
prot_id = ICE_PROT_UDP_OF;
break;
flds[fld].xtrct.disp = (u8)(ice_flds_info[fld].off % ese_bits);
flds[fld].xtrct.idx = params->es_cnt;
flds[fld].xtrct.mask = ice_flds_info[fld].mask;
+ if (prot_id == ICE_PROT_IPV6_NEXT_PROTO) {
+ flds[fld].xtrct.off = 0;
+ flds[fld].xtrct.disp = 0;
+ }
/* Adjust the next field-entry index after accommodating the number of
* entries this field consumes
/* Add a HW profile for this flow profile */
status = ice_add_prof(hw, blk, prof_id, (u8 *)params->ptypes,
params->attr, params->attr_cnt, params->es,
- params->mask);
+ params->mask, true);
if (status) {
ice_debug(hw, ICE_DBG_FLOW, "Error adding a HW flow profile\n");
goto out;
return status;
}
+#define FLAG_GTP_EH_PDU_LINK BIT_ULL(13)
+#define FLAG_GTP_EH_PDU BIT_ULL(14)
+
+#define FLAG_GTPU_MSK \
+ (FLAG_GTP_EH_PDU | FLAG_GTP_EH_PDU_LINK)
+#define FLAG_GTPU_UP \
+ (FLAG_GTP_EH_PDU | FLAG_GTP_EH_PDU_LINK)
+#define FLAG_GTPU_DW \
+ (FLAG_GTP_EH_PDU)
+/**
+ * ice_flow_set_hw_prof - Set HW flow profile based on the parsed profile info
+ * @hw: pointer to the HW struct
+ * @dest_vsi_handle: dest VSI handle
+ * @fdir_vsi_handle: fdir programming VSI handle
+ * @prof: stores parsed profile info from raw flow
+ * @blk: classification stage
+ */
+enum ice_status
+ice_flow_set_hw_prof(struct ice_hw *hw, u16 dest_vsi_handle,
+ u16 fdir_vsi_handle, struct ice_parser_profile *prof,
+ enum ice_block blk)
+{
+ int id = ice_find_first_bit(prof->ptypes, UINT16_MAX);
+ struct ice_flow_prof_params *params;
+ u8 fv_words = hw->blk[blk].es.fvw;
+ enum ice_status status;
+ u16 vsi_num;
+ int i, idx;
+
+ params = (struct ice_flow_prof_params *)ice_malloc(hw, sizeof(*params));
+ if (!params)
+ return ICE_ERR_NO_MEMORY;
+
+ for (i = 0; i < ICE_MAX_FV_WORDS; i++) {
+ params->es[i].prot_id = ICE_PROT_INVALID;
+ params->es[i].off = ICE_FV_OFFSET_INVAL;
+ }
+
+ for (i = 0; i < prof->fv_num; i++) {
+ if (hw->blk[blk].es.reverse)
+ idx = fv_words - i - 1;
+ else
+ idx = i;
+ params->es[idx].prot_id = prof->fv[i].proto_id;
+ params->es[idx].off = prof->fv[i].offset;
+ params->mask[idx] = CPU_TO_BE16(prof->fv[i].msk);
+ }
+
+ switch (prof->flags) {
+ case FLAG_GTPU_DW:
+ params->attr = ice_attr_gtpu_down;
+ params->attr_cnt = ARRAY_SIZE(ice_attr_gtpu_down);
+ break;
+ case FLAG_GTPU_UP:
+ params->attr = ice_attr_gtpu_up;
+ params->attr_cnt = ARRAY_SIZE(ice_attr_gtpu_up);
+ break;
+ default:
+ if (prof->flags_msk & FLAG_GTPU_MSK) {
+ params->attr = ice_attr_gtpu_session;
+ params->attr_cnt = ARRAY_SIZE(ice_attr_gtpu_session);
+ }
+ break;
+ }
+
+ status = ice_add_prof(hw, blk, id, (u8 *)prof->ptypes,
+ params->attr, params->attr_cnt,
+ params->es, params->mask, false);
+ if (status)
+ goto free_params;
+
+ status = ice_flow_assoc_hw_prof(hw, blk, dest_vsi_handle,
+ fdir_vsi_handle, id);
+ if (status)
+ goto free_params;
+
+ return ICE_SUCCESS;
+
+free_params:
+ ice_free(hw, params);
+
+ return status;
+}
+
/**
* ice_flow_add_prof - Add a flow profile for packet segments and matched fields
* @hw: pointer to the HW struct
}
}
+/**
+ * ice_rss_cfg_raw_symm - configure symmetric hash parameters
+ * for raw pattern
+ * @hw: pointer to the hardware structure
+ * @prof: pointer to parser profile
+ * @prof_id: profile ID
+ *
+ * Calculate symmetric hash parameters based on input protocol type.
+ */
+static void
+ice_rss_cfg_raw_symm(struct ice_hw *hw,
+ struct ice_parser_profile *prof, u64 prof_id)
+{
+ u8 src_idx, dst_idx, proto_id;
+ int len, i = 0;
+
+ while (i < prof->fv_num) {
+ proto_id = prof->fv[i].proto_id;
+
+ switch (proto_id) {
+ case ICE_PROT_IPV4_OF_OR_S:
+ len = ICE_FLOW_FLD_SZ_IPV4_ADDR /
+ ICE_FLOW_FV_EXTRACT_SZ;
+ if (prof->fv[i].offset ==
+ ICE_FLOW_FIELD_IPV4_SRC_OFFSET &&
+ prof->fv[i + len].proto_id == proto_id &&
+ prof->fv[i + len].offset ==
+ ICE_FLOW_FIELD_IPV4_DST_OFFSET) {
+ src_idx = i;
+ dst_idx = i + len;
+ i += 2 * len;
+ break;
+ }
+ i++;
+ continue;
+ case ICE_PROT_IPV6_OF_OR_S:
+ len = ICE_FLOW_FLD_SZ_IPV6_ADDR /
+ ICE_FLOW_FV_EXTRACT_SZ;
+ if (prof->fv[i].offset ==
+ ICE_FLOW_FIELD_IPV6_SRC_OFFSET &&
+ prof->fv[i + len].proto_id == proto_id &&
+ prof->fv[i + len].offset ==
+ ICE_FLOW_FIELD_IPV6_DST_OFFSET) {
+ src_idx = i;
+ dst_idx = i + len;
+ i += 2 * len;
+ break;
+ }
+ i++;
+ continue;
+ case ICE_PROT_TCP_IL:
+ case ICE_PROT_UDP_IL_OR_S:
+ case ICE_PROT_SCTP_IL:
+ len = ICE_FLOW_FLD_SZ_PORT /
+ ICE_FLOW_FV_EXTRACT_SZ;
+ if (prof->fv[i].offset ==
+ ICE_FLOW_FIELD_SRC_PORT_OFFSET &&
+ prof->fv[i + len].proto_id == proto_id &&
+ prof->fv[i + len].offset ==
+ ICE_FLOW_FIELD_DST_PORT_OFFSET) {
+ src_idx = i;
+ dst_idx = i + len;
+ i += 2 * len;
+ break;
+ }
+ i++;
+ continue;
+ default:
+ i++;
+ continue;
+ }
+ ice_rss_config_xor(hw, prof_id, src_idx, dst_idx, len);
+ }
+}
+
+/* Max registers index per packet profile */
+#define ICE_SYMM_REG_INDEX_MAX 6
+
+/**
+ * ice_rss_update_raw_symm - update symmetric hash configuration
+ * for raw pattern
+ * @hw: pointer to the hardware structure
+ * @cfg: configure parameters for raw pattern
+ * @id: profile tracking ID
+ *
+ * Update symmetric hash configuration for raw pattern if required.
+ * Otherwise only clear to default.
+ */
+void
+ice_rss_update_raw_symm(struct ice_hw *hw,
+ struct ice_rss_raw_cfg *cfg, u64 id)
+{
+ struct ice_prof_map *map;
+ u8 prof_id, m;
+
+ ice_acquire_lock(&hw->blk[ICE_BLK_RSS].es.prof_map_lock);
+ map = ice_search_prof_id(hw, ICE_BLK_RSS, id);
+ if (map)
+ prof_id = map->prof_id;
+ ice_release_lock(&hw->blk[ICE_BLK_RSS].es.prof_map_lock);
+ if (!map)
+ return;
+ /* clear to default */
+ for (m = 0; m < ICE_SYMM_REG_INDEX_MAX; m++)
+ wr32(hw, GLQF_HSYMM(prof_id, m), 0);
+ if (cfg->symm)
+ ice_rss_cfg_raw_symm(hw, &cfg->prof, prof_id);
+}
+
/**
* ice_add_rss_cfg_sync - add an RSS configuration
* @hw: pointer to the hardware structure
git.droids-corp.org / dpdk.git / blobdiff