net/ice/base: group function prototypes together

[dpdk.git] / drivers / net / ice / base / ice_hw_autogen.h

diff --git a/drivers/net/ice/base/ice_hw_autogen.h b/drivers/net/ice/base/ice_hw_autogen.h
index 2b423ba..572f481 100644 (file)
--- a/drivers/net/ice/base/ice_hw_autogen.h
+++ b/drivers/net/ice/base/ice_hw_autogen.h
@@ -1,13 +1,11 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2019
+ * Copyright(c) 2001-2020 Intel Corporation
  */
 
 /* Machine-generated file; do not edit */
 #ifndef _ICE_HW_AUTOGEN_H_
 #define _ICE_HW_AUTOGEN_H_
 
-
-
 #define GL_RDPU_CNTRL                          0x00052054 /* Reset Source: CORER */
 #define GL_RDPU_CNTRL_RX_PAD_EN_S              0
 #define GL_RDPU_CNTRL_RX_PAD_EN_M              BIT(0)
@@ -5234,8 +5232,8 @@
 #define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)
 #define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3800 + ((_i) * 32)) /* _i=0...8 */ /* Reset Source: GLOBR */
 #define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX 8
-#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_S 0
-#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M MAKEMASK(0xFFFF, 0)
+#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_S 0
+#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M MAKEMASK(0xFFFF, 0)
 #define PRTMAC_HSEC_CTL_TX_SA_PART1            0x001E3960 /* Reset Source: GLOBR */
 #define PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_S 0
 #define PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_M MAKEMASK(0xFFFFFFFF, 0)
@@ -5330,6 +5328,29 @@
 #define GL_MDCK_RX                             0x0029422C /* Reset Source: CORER */
 #define GL_MDCK_RX_DESC_ADDR_S                 0
 #define GL_MDCK_RX_DESC_ADDR_M                 BIT(0)
+#define GL_MDCK_TX_TDPU                                0x00049348 /* Reset Source: CORER */
+#define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_S      0
+#define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_M      BIT(0)
+#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_S 1
+#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1)
+#define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_S      2
+#define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_M      BIT(2)
+#define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_S   3
+#define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_M   BIT(3)
+#define GL_MDCK_TX_TDPU_MAL_CMD_ITR_DIS_S      4
+#define GL_MDCK_TX_TDPU_MAL_CMD_ITR_DIS_M      BIT(4)
+#define GL_MDCK_TX_TDPU_BIG_PKT_SIZE_ITR_DIS_S 5
+#define GL_MDCK_TX_TDPU_BIG_PKT_SIZE_ITR_DIS_M BIT(5)
+#define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_S 6
+#define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_M BIT(6)
+#define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_S      7
+#define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_M      BIT(7)
+#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_S 8
+#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_M BIT(8)
+#define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_S 9
+#define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_M BIT(9)
+#define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_S    10
+#define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_M    BIT(10)
 #define GL_MDET_RX                             0x00294C00 /* Reset Source: CORER */
 #define GL_MDET_RX_QNUM_S                      0
 #define GL_MDET_RX_QNUM_M                      MAKEMASK(0x7FFF, 0)
@@ -5363,6 +5384,17 @@
 #define GL_MDET_TX_TCLAN_MAL_TYPE_M            MAKEMASK(0x1F, 26)
 #define GL_MDET_TX_TCLAN_VALID_S               31
 #define GL_MDET_TX_TCLAN_VALID_M               BIT(31)
+#define GL_MDET_TX_TDPU                                0x00049350 /* Reset Source: CORER */
+#define GL_MDET_TX_TDPU_QNUM_S                 0
+#define GL_MDET_TX_TDPU_QNUM_M                 MAKEMASK(0x7FFF, 0)
+#define GL_MDET_TX_TDPU_VF_NUM_S               15
+#define GL_MDET_TX_TDPU_VF_NUM_M               MAKEMASK(0xFF, 15)
+#define GL_MDET_TX_TDPU_PF_NUM_S               23
+#define GL_MDET_TX_TDPU_PF_NUM_M               MAKEMASK(0x7, 23)
+#define GL_MDET_TX_TDPU_MAL_TYPE_S             26
+#define GL_MDET_TX_TDPU_MAL_TYPE_M             MAKEMASK(0x1F, 26)
+#define GL_MDET_TX_TDPU_VALID_S                        31
+#define GL_MDET_TX_TDPU_VALID_M                        BIT(31)
 #define GLRLAN_MDET                            0x00294200 /* Reset Source: CORER */
 #define GLRLAN_MDET_PCKT_EXTRCT_ERR_S          0
 #define GLRLAN_MDET_PCKT_EXTRCT_ERR_M          BIT(0)