net/ice/base: support NVM access commands

[dpdk.git] / drivers / net / ice / base / ice_lan_tx_rx.h

diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h
index 4a1ea0c..2cba6bc 100644 (file)
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2018
+ * Copyright(c) 2001-2019
  */
 
 #ifndef _ICE_LAN_TX_RX_H_
@@ -162,7 +162,7 @@ struct ice_fltr_desc {
 
 #define ICE_FXD_FLTR_QW1_FDID_PRI_S    25
 #define ICE_FXD_FLTR_QW1_FDID_PRI_M    (0x7ULL << ICE_FXD_FLTR_QW1_FDID_PRI_S)
-#define ICE_FXD_FLTR_QW1_FDID_PRI_ZERO 0x0ULL
+#define ICE_FXD_FLTR_QW1_FDID_PRI_ONE  0x1ULL
 
 #define ICE_FXD_FLTR_QW1_FDID_MDID_S   28
 #define ICE_FXD_FLTR_QW1_FDID_MDID_M   (0xFULL << ICE_FXD_FLTR_QW1_FDID_MDID_S)
@@ -606,6 +606,12 @@ enum ice_rxdid {
        ICE_RXDID_FLEX_NIC              = 2,
        ICE_RXDID_FLEX_NIC_2            = 6,
        ICE_RXDID_HW                    = 7,
+       ICE_RXDID_COMMS_GENERIC         = 16,
+       ICE_RXDID_COMMS_AUX_VLAN        = 17,
+       ICE_RXDID_COMMS_AUX_IPV4        = 18,
+       ICE_RXDID_COMMS_AUX_IPV6        = 19,
+       ICE_RXDID_COMMS_AUX_IPV6_FLOW   = 20,
+       ICE_RXDID_COMMS_AUX_TCP         = 21,
        ICE_RXDID_LAST                  = 63,
 };
 
@@ -627,39 +633,60 @@ enum ice_flex_opcode {
        ICE_RX_OPC_PROTID
 };
 
-/* Receive Descriptor MDID values */
-enum ice_flex_rx_mdid {
-       ICE_RX_MDID_FLOW_ID_LOWER       = 5,
-       ICE_RX_MDID_FLOW_ID_HIGH,
-       ICE_RX_MDID_DST_VSI             = 13,
-       ICE_RX_MDID_SRC_VSI             = 19,
-       ICE_RX_MDID_HASH_LOW            = 56,
-       ICE_RX_MDID_HASH_HIGH,
-       ICE_RX_MDID_ACL_CTR0            = ICE_RX_MDID_HASH_LOW,
-       ICE_RX_MDID_ACL_CTR1            = ICE_RX_MDID_HASH_HIGH,
-       ICE_RX_MDID_ACL_CTR2            = 59
+/* Receive Descriptor MDID values that access packet flags */
+enum ice_flex_mdid_pkt_flags {
+       ICE_RX_MDID_PKT_FLAGS_15_0      = 20,
+       ICE_RX_MDID_PKT_FLAGS_31_16,
+       ICE_RX_MDID_PKT_FLAGS_47_32,
+       ICE_RX_MDID_PKT_FLAGS_63_48,
+};
+
+/* Generic descriptor MDID values */
+enum ice_flex_mdid {
+       ICE_MDID_GENERIC_WORD_0,
+       ICE_MDID_GENERIC_WORD_1,
+       ICE_MDID_GENERIC_WORD_2,
+       ICE_MDID_GENERIC_WORD_3,
+       ICE_MDID_GENERIC_WORD_4,
+       ICE_MDID_FLOW_ID_LOWER,
+       ICE_MDID_FLOW_ID_HIGH,
+       ICE_MDID_RX_DESCR_PROF_IDX,
+       ICE_MDID_RX_PKT_DROP,
+       ICE_MDID_RX_DST_Q               = 12,
+       ICE_MDID_RX_DST_VSI,
+       ICE_MDID_SRC_VSI                = 19,
+       ICE_MDID_ACL_NOP                = 55,
+       /* Entry 56 */
+       ICE_MDID_RX_HASH_LOW,
+       ICE_MDID_ACL_CNTR_PKT           = ICE_MDID_RX_HASH_LOW,
+       /* Entry 57 */
+       ICE_MDID_RX_HASH_HIGH,
+       ICE_MDID_ACL_CNTR_BYTES         = ICE_MDID_RX_HASH_HIGH,
+       ICE_MDID_ACL_CNTR_PKT_BYTES
 };
 
 /* for ice_32byte_rx_flex_desc.mir_id_umb_cast member */
 #define ICE_RX_FLEX_DESC_MIRROR_M      (0x3F) /* 6-bits */
 
-/* Rx Flag64 packet flag bits */
-enum ice_rx_flg64_bits {
-       ICE_RXFLG_PKT_DSI       = 0,
-       ICE_RXFLG_EVLAN_x8100   = 15,
-       ICE_RXFLG_EVLAN_x9100,
-       ICE_RXFLG_VLAN_x8100,
-       ICE_RXFLG_TNL_MAC       = 22,
-       ICE_RXFLG_TNL_VLAN,
-       ICE_RXFLG_PKT_FRG,
-       ICE_RXFLG_FIN           = 32,
-       ICE_RXFLG_SYN,
-       ICE_RXFLG_RST,
-       ICE_RXFLG_TNL0          = 38,
-       ICE_RXFLG_TNL1,
-       ICE_RXFLG_TNL2,
-       ICE_RXFLG_UDP_GRE,
-       ICE_RXFLG_RSVD          = 63
+/* Rx/Tx Flag64 packet flag bits */
+enum ice_flg64_bits {
+       ICE_FLG_PKT_DSI         = 0,
+       /* If there is a 1 in this bit position then that means Rx packet */
+       ICE_FLG_PKT_DIR         = 4,
+       ICE_FLG_EVLAN_x8100     = 15,
+       ICE_FLG_EVLAN_x9100,
+       ICE_FLG_VLAN_x8100,
+       ICE_FLG_TNL_MAC         = 22,
+       ICE_FLG_TNL_VLAN,
+       ICE_FLG_PKT_FRG,
+       ICE_FLG_FIN             = 32,
+       ICE_FLG_SYN,
+       ICE_FLG_RST,
+       ICE_FLG_TNL0            = 38,
+       ICE_FLG_TNL1,
+       ICE_FLG_TNL2,
+       ICE_FLG_UDP_GRE,
+       ICE_FLG_RSVD            = 63
 };
 
 enum ice_rx_flex_desc_umb_cast_bits { /* field is 2 bits long */
@@ -786,6 +813,7 @@ struct ice_rlan_ctx {
        u8 tphdata_ena;
        u8 tphhead_ena;
        u16 lrxqthresh; /* bigger than needed, see above for reason */
+       u8 prefena;     /* NOTE: normally must be set to 1 at init */
 };
 
 struct ice_ctx_ele {
@@ -987,6 +1015,7 @@ struct ice_tlan_ctx {
 #define ICE_TLAN_CTX_VMVF_TYPE_PF      2
        u16 src_vsi;
        u8 tsyn_ena;
+       u8 internal_usage_flag;
        u8 alt_vlan;
        u16 cpuid;              /* bigger than needed, see above for reason */
        u8 wb_mode;