net/ice/base: fix inner L4 offset for GTPU dummy packet

[dpdk.git] / drivers / net / ice / base / ice_lan_tx_rx.h

diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h
index d904385..696c6a3 100644 (file)
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2020
+ * Copyright(c) 2001-2021 Intel Corporation
  */
 
 #ifndef _ICE_LAN_TX_RX_H_
@@ -175,6 +175,50 @@ struct ice_fltr_desc {
                        (0xFFFFFFFFULL << ICE_FXD_FLTR_QW1_FDID_S)
 #define ICE_FXD_FLTR_QW1_FDID_ZERO     0x0ULL
 
+/* definition for FD filter programming status descriptor WB format */
+#define ICE_FXD_FLTR_WB_QW0_BUKT_LEN_S 28
+#define ICE_FXD_FLTR_WB_QW0_BUKT_LEN_M \
+                       (0xFULL << ICE_FXD_FLTR_WB_QW0_BUKT_LEN_S)
+
+#define ICE_FXD_FLTR_WB_QW0_FLTR_STAT_S        32
+#define ICE_FXD_FLTR_WB_QW0_FLTR_STAT_M        \
+                       (0xFFFFFFFFULL << ICE_FXD_FLTR_WB_QW0_FLTR_STAT_S)
+
+#define ICE_FXD_FLTR_WB_QW1_DD_S       0
+#define ICE_FXD_FLTR_WB_QW1_DD_M       (0x1ULL << ICE_FXD_FLTR_WB_QW1_DD_S)
+#define ICE_FXD_FLTR_WB_QW1_DD_YES     0x1ULL
+
+#define ICE_FXD_FLTR_WB_QW1_PROG_ID_S  1
+#define ICE_FXD_FLTR_WB_QW1_PROG_ID_M  \
+                               (0x3ULL << ICE_FXD_FLTR_WB_QW1_PROG_ID_S)
+#define ICE_FXD_FLTR_WB_QW1_PROG_ADD   0x0ULL
+#define ICE_FXD_FLTR_WB_QW1_PROG_DEL   0x1ULL
+
+#define ICE_FXD_FLTR_WB_QW1_FAIL_S     4
+#define ICE_FXD_FLTR_WB_QW1_FAIL_M     (0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_S)
+#define ICE_FXD_FLTR_WB_QW1_FAIL_YES   0x1ULL
+
+#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S        5
+#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_M        \
+                               (0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S)
+#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_YES      0x1ULL
+
+#define ICE_FXD_FLTR_WB_QW1_FLT_ADDR_S 8
+#define ICE_FXD_FLTR_WB_QW1_FLT_ADDR_M \
+                               (0x3FFFULL << ICE_FXD_FLTR_WB_QW1_FLT_ADDR_S)
+
+#define ICE_FXD_FLTR_WB_QW1_PKT_PROF_S 28
+#define ICE_FXD_FLTR_WB_QW1_PKT_PROF_M \
+                               (0x7FULL << ICE_FXD_FLTR_WB_QW1_PKT_PROF_S)
+
+#define ICE_FXD_FLTR_WB_QW1_BUKT_HASH_S        38
+#define ICE_FXD_FLTR_WB_QW1_BUKT_HASH_M        \
+                               (0x3FFFFFF << ICE_FXD_FLTR_WB_QW1_BUKT_HASH_S)
+
+#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_M        \
+                               (0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S)
+#define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_YES      0x1ULL
+
 enum ice_rx_desc_status_bits {
        /* Note: These are predefined bit offsets */
        ICE_RX_DESC_STATUS_DD_S                 = 0,
@@ -252,7 +296,6 @@ enum ice_rx_l2_ptype {
 };
 
 struct ice_rx_ptype_decoded {
-       u32 ptype:10;
        u32 known:1;
        u32 outer_ip:1;
        u32 outer_ip_ver:2;
@@ -671,6 +714,7 @@ enum ice_rxdid {
        ICE_RXDID_COMMS_AUX_IPV6        = 19,
        ICE_RXDID_COMMS_AUX_IPV6_FLOW   = 20,
        ICE_RXDID_COMMS_AUX_TCP         = 21,
+       ICE_RXDID_COMMS_AUX_IP_OFFSET   = 25,
        ICE_RXDID_LAST                  = 63,
 };
 
@@ -1091,7 +1135,7 @@ struct ice_tlan_ctx {
        u8 drop_ena;
        u8 cache_prof_idx;
        u8 pkt_shaper_prof_idx;
-       u8 int_q_state; /* width not needed - internal do not write */
+       u8 int_q_state; /* width not needed - internal - DO NOT WRITE!!! */
 };
 
 /* LAN Tx Completion Queue data */
@@ -1104,7 +1148,6 @@ struct ice_tx_cmpltnq {
 };
 #pragma pack()
 
-
 /* LAN Tx Completion Queue Context */
 #pragma pack(1)
 struct ice_tx_cmpltnq_ctx {
@@ -1173,8 +1216,7 @@ struct ice_tx_drbell_q_ctx {
 
 /* macro to make the table lines short */
 #define ICE_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
-       {       PTYPE, \
-               1, \
+       {       1, \
                ICE_RX_PTYPE_OUTER_##OUTER_IP, \
                ICE_RX_PTYPE_OUTER_##OUTER_IP_VER, \
                ICE_RX_PTYPE_##OUTER_FRAG, \
@@ -1184,18 +1226,18 @@ struct ice_tx_drbell_q_ctx {
                ICE_RX_PTYPE_INNER_PROT_##I, \
                ICE_RX_PTYPE_PAYLOAD_LAYER_##PL }
 
-#define ICE_PTT_UNUSED_ENTRY(PTYPE) { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+#define ICE_PTT_UNUSED_ENTRY(PTYPE) { 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 
 /* shorter macros makes the table fit but are terse */
 #define ICE_RX_PTYPE_NOF               ICE_RX_PTYPE_NOT_FRAG
 #define ICE_RX_PTYPE_FRG               ICE_RX_PTYPE_FRAG
 
-/* Lookup table mapping the HW PTYPE to the bit field for decoding */
-static const struct ice_rx_ptype_decoded ice_ptype_lkup[] = {
+/* Lookup table mapping the 10-bit HW PTYPE to the bit field for decoding */
+static const struct ice_rx_ptype_decoded ice_ptype_lkup[1024] = {
        /* L2 Packet types */
        ICE_PTT_UNUSED_ENTRY(0),
        ICE_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
-       ICE_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
+       ICE_PTT_UNUSED_ENTRY(2),
        ICE_PTT_UNUSED_ENTRY(3),
        ICE_PTT_UNUSED_ENTRY(4),
        ICE_PTT_UNUSED_ENTRY(5),
@@ -1309,7 +1351,7 @@ static const struct ice_rx_ptype_decoded ice_ptype_lkup[] = {
        /* Non Tunneled IPv6 */
        ICE_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
        ICE_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
-       ICE_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY3),
+       ICE_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
        ICE_PTT_UNUSED_ENTRY(91),
        ICE_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
        ICE_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),