net/ice/base: do not wait for PE unit to load

[dpdk.git] / drivers / net / ice / base / ice_lan_tx_rx.h

diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h
index 7c3927a..a97c63c 100644 (file)
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -173,7 +173,6 @@ struct ice_fltr_desc {
                        (0xFFFFFFFFULL << ICE_FXD_FLTR_QW1_FDID_S)
 #define ICE_FXD_FLTR_QW1_FDID_ZERO     0x0ULL
 
-
 enum ice_rx_desc_status_bits {
        /* Note: These are predefined bit offsets */
        ICE_RX_DESC_STATUS_DD_S                 = 0,
@@ -204,7 +203,6 @@ enum ice_rx_desc_status_bits {
 #define ICE_RXD_QW1_STATUS_TSYNVALID_S ICE_RX_DESC_STATUS_TSYNVALID_S
 #define ICE_RXD_QW1_STATUS_TSYNVALID_M BIT_ULL(ICE_RXD_QW1_STATUS_TSYNVALID_S)
 
-
 enum ice_rx_desc_fltstat_values {
        ICE_RX_DESC_FLTSTAT_NO_DATA     = 0,
        ICE_RX_DESC_FLTSTAT_RSV_FD_ID   = 1, /* 16byte desc? FD_ID : RSV */
@@ -212,7 +210,6 @@ enum ice_rx_desc_fltstat_values {
        ICE_RX_DESC_FLTSTAT_RSS_HASH    = 3,
 };
 
-
 #define ICE_RXD_QW1_ERROR_S    19
 #define ICE_RXD_QW1_ERROR_M            (0xFFUL << ICE_RXD_QW1_ERROR_S)
 
@@ -310,7 +307,6 @@ enum ice_rx_ptype_payload_layer {
        ICE_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
 };
 
-
 #define ICE_RXD_QW1_LEN_PBUF_S 38
 #define ICE_RXD_QW1_LEN_PBUF_M (0x3FFFULL << ICE_RXD_QW1_LEN_PBUF_S)
 
@@ -320,7 +316,6 @@ enum ice_rx_ptype_payload_layer {
 #define ICE_RXD_QW1_LEN_SPH_S  63
 #define ICE_RXD_QW1_LEN_SPH_M  BIT_ULL(ICE_RXD_QW1_LEN_SPH_S)
 
-
 enum ice_rx_desc_ext_status_bits {
        /* Note: These are predefined bit offsets */
        ICE_RX_DESC_EXT_STATUS_L2TAG2P_S        = 0,
@@ -331,7 +326,6 @@ enum ice_rx_desc_ext_status_bits {
        ICE_RX_DESC_EXT_STATUS_PELONGB_S        = 11,
 };
 
-
 enum ice_rx_desc_pe_status_bits {
        /* Note: These are predefined bit offsets */
        ICE_RX_DESC_PE_STATUS_QPID_S            = 0, /* 18 BITS */
@@ -352,7 +346,6 @@ enum ice_rx_desc_pe_status_bits {
 #define ICE_RX_PROG_STATUS_DESC_QW1_PROGID_M   \
                        (0x7UL << ICE_RX_PROG_STATUS_DESC_QW1_PROGID_S)
 
-
 #define ICE_RX_PROG_STATUS_DESC_QW1_ERROR_S    19
 #define ICE_RX_PROG_STATUS_DESC_QW1_ERROR_M    \
                        (0x3FUL << ICE_RX_PROG_STATUS_DESC_QW1_ERROR_S)
@@ -619,6 +612,46 @@ struct ice_32b_rx_flex_desc_nic_2 {
        } flex_ts;
 };
 
+/* Rx Flex Descriptor for Comms Package Profile
+ * RxDID Profile ID 16-21
+ * Flex-field 0: RSS hash lower 16-bits
+ * Flex-field 1: RSS hash upper 16-bits
+ * Flex-field 2: Flow ID lower 16-bits
+ * Flex-field 3: Flow ID upper 16-bits
+ * Flex-field 4: AUX0
+ * Flex-field 5: AUX1
+ */
+struct ice_32b_rx_flex_desc_comms {
+       /* Qword 0 */
+       u8 rxdid;
+       u8 mir_id_umb_cast;
+       __le16 ptype_flexi_flags0;
+       __le16 pkt_len;
+       __le16 hdr_len_sph_flex_flags1;
+
+       /* Qword 1 */
+       __le16 status_error0;
+       __le16 l2tag1;
+       __le32 rss_hash;
+
+       /* Qword 2 */
+       __le16 status_error1;
+       u8 flexi_flags2;
+       u8 ts_low;
+       __le16 l2tag2_1st;
+       __le16 l2tag2_2nd;
+
+       /* Qword 3 */
+       __le32 flow_id;
+       union {
+               struct {
+                       __le16 aux0;
+                       __le16 aux1;
+               } flex;
+               __le32 ts_high;
+       } flex_ts;
+};
+
 /* Receive Flex Descriptor profile IDs: There are a total
  * of 64 profiles where profile IDs 0/1 are for legacy; and
  * profiles 2-63 are flex profiles that can be programmed
@@ -697,7 +730,7 @@ enum ice_flg64_bits {
        ICE_FLG_PKT_DSI         = 0,
        /* If there is a 1 in this bit position then that means Rx packet */
        ICE_FLG_PKT_DIR         = 4,
-       ICE_FLG_EVLAN_x8100     = 15,
+       ICE_FLG_EVLAN_x8100     = 14,
        ICE_FLG_EVLAN_x9100,
        ICE_FLG_VLAN_x8100,
        ICE_FLG_TNL_MAC         = 22,
@@ -800,7 +833,6 @@ enum ice_rx_flex_desc_exstat_bits {
        ICE_RX_FLEX_DESC_EXSTAT_OVERSIZE_S = 3,
 };
 
-
 #define ICE_RXQ_CTX_SIZE_DWORDS                8
 #define ICE_RXQ_CTX_SZ                 (ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32))
 #define ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS 22
@@ -1016,7 +1048,6 @@ enum ice_tx_ctx_desc_eipt_offload {
 #define ICE_TXD_CTX_QW0_L4T_CS_S       23
 #define ICE_TXD_CTX_QW0_L4T_CS_M       BIT_ULL(ICE_TXD_CTX_QW0_L4T_CS_S)
 
-
 #define ICE_LAN_TXQ_MAX_QGRPS  127
 #define ICE_LAN_TXQ_MAX_QDIS   1023