net/ice/base: whitelist register for NVM access

[dpdk.git] / drivers / net / ice / base / ice_nvm.c

diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c
index e009425..2d92524 100644 (file)
--- a/drivers/net/ice/base/ice_nvm.c
+++ b/drivers/net/ice/base/ice_nvm.c
@@ -260,8 +260,8 @@ enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)
  */
 enum ice_status ice_init_nvm(struct ice_hw *hw)
 {
-       struct ice_nvm_info *nvm = &hw->nvm;
        u16 oem_hi, oem_lo, boot_cfg_tlv, boot_cfg_tlv_len;
+       struct ice_nvm_info *nvm = &hw->nvm;
        u16 eetrack_lo, eetrack_hi;
        enum ice_status status;
        u32 fla, gens_stat;
@@ -504,6 +504,7 @@ ice_validate_nvm_rw_reg(struct ice_nvm_access_cmd *cmd)
        case GL_FWSTS:
        case GL_MNG_FWSM:
        case GLGEN_CSR_DEBUG_C:
+       case GLGEN_RSTAT:
        case GLPCI_LBARCTRL:
        case GLNVM_GENS:
        case GLNVM_FLA:
@@ -579,9 +580,14 @@ ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
        if (status)
                return status;
 
-       /* The HICR_EN register is read-only */
-       if (cmd->offset == GL_HICR_EN)
+       /* Reject requests to write to read-only registers */
+       switch (cmd->offset) {
+       case GL_HICR_EN:
+       case GLGEN_RSTAT:
                return ICE_ERR_OUT_OF_RANGE;
+       default:
+               break;
+       }
 
        ice_debug(hw, ICE_DBG_NVM,
                  "NVM access: writing register %08x with value %08x\n",