net/ice: fix race condition in Rx timestamp

[dpdk.git] / drivers / net / ice / base / ice_nvm.c

diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c
index 71affd1..7860006 100644 (file)
--- a/drivers/net/ice/base/ice_nvm.c
+++ b/drivers/net/ice/base/ice_nvm.c
@@ -1,9 +1,11 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2020 Intel Corporation
+ * Copyright(c) 2001-2021 Intel Corporation
  */
 
 #include "ice_common.h"
 
+#define GL_MNG_DEF_DEVID 0x000B611C
+
 /**
  * ice_aq_read_nvm
  * @hw: pointer to the HW struct
@@ -348,6 +350,22 @@ ice_read_nvm_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u1
        return status;
 }
 
+/**
+ * ice_read_nvm_sr_copy - Read a word from the Shadow RAM copy in the NVM bank
+ * @hw: pointer to the HW structure
+ * @bank: whether to read from the active or inactive NVM module
+ * @offset: offset into the Shadow RAM copy to read, in words
+ * @data: storage for returned word value
+ *
+ * Read the specified word from the copy of the Shadow RAM found in the
+ * specified NVM module.
+ */
+static enum ice_status
+ice_read_nvm_sr_copy(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)
+{
+       return ice_read_nvm_module(hw, bank, ICE_NVM_SR_COPY_WORD_OFFSET + offset, data);
+}
+
 /**
  * ice_read_orom_module - Read from the active Option ROM module
  * @hw: pointer to the HW structure
@@ -549,31 +567,33 @@ static enum ice_status ice_get_nvm_srev(struct ice_hw *hw, enum ice_bank_select
 /**
  * ice_get_nvm_ver_info - Read NVM version information
  * @hw: pointer to the HW struct
+ * @bank: whether to read from the active or inactive flash bank
  * @nvm: pointer to NVM info structure
  *
  * Read the NVM EETRACK ID and map version of the main NVM image bank, filling
  * in the nvm info structure.
  */
 static enum ice_status
-ice_get_nvm_ver_info(struct ice_hw *hw, struct ice_nvm_info *nvm)
+ice_get_nvm_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_nvm_info *nvm)
 {
        u16 eetrack_lo, eetrack_hi, ver;
        enum ice_status status;
 
-       status = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &ver);
+       status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_DEV_STARTER_VER, &ver);
        if (status) {
                ice_debug(hw, ICE_DBG_NVM, "Failed to read DEV starter version.\n");
                return status;
        }
+
        nvm->major = (ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT;
        nvm->minor = (ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT;
 
-       status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_LO, &eetrack_lo);
+       status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_LO, &eetrack_lo);
        if (status) {
                ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK lo.\n");
                return status;
        }
-       status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_HI, &eetrack_hi);
+       status = ice_read_nvm_sr_copy(hw, bank, ICE_SR_NVM_EETRACK_HI, &eetrack_hi);
        if (status) {
                ice_debug(hw, ICE_DBG_NVM, "Failed to read EETRACK hi.\n");
                return status;
@@ -581,13 +601,27 @@ ice_get_nvm_ver_info(struct ice_hw *hw, struct ice_nvm_info *nvm)
 
        nvm->eetrack = (eetrack_hi << 16) | eetrack_lo;
 
-       status = ice_get_nvm_srev(hw, ICE_ACTIVE_FLASH_BANK, &nvm->srev);
+       status = ice_get_nvm_srev(hw, bank, &nvm->srev);
        if (status)
                ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM security revision.\n");
 
        return ICE_SUCCESS;
 }
 
+/**
+ * ice_get_inactive_nvm_ver - Read Option ROM version from the inactive bank
+ * @hw: pointer to the HW structure
+ * @nvm: storage for Option ROM version information
+ *
+ * Reads the NVM EETRACK ID, Map version, and security revision of the
+ * inactive NVM bank. Used to access version data for a pending update that
+ * has not yet been activated.
+ */
+enum ice_status ice_get_inactive_nvm_ver(struct ice_hw *hw, struct ice_nvm_info *nvm)
+{
+       return ice_get_nvm_ver_info(hw, ICE_INACTIVE_FLASH_BANK, nvm);
+}
+
 /**
  * ice_get_orom_srev - Read the security revision from the OROM CSS header
  * @hw: pointer to the HW struct
@@ -976,7 +1010,7 @@ enum ice_status ice_init_nvm(struct ice_hw *hw)
                return status;
        }
 
-       status = ice_get_nvm_ver_info(hw, &flash->nvm);
+       status = ice_get_nvm_ver_info(hw, ICE_ACTIVE_FLASH_BANK, &flash->nvm);
        if (status) {
                ice_debug(hw, ICE_DBG_INIT, "Failed to read NVM info.\n");
                return status;
@@ -1045,6 +1079,34 @@ enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw)
        return status;
 }
 
+/**
+ * ice_nvm_recalculate_checksum
+ * @hw: pointer to the HW struct
+ *
+ * Recalculate NVM PFA checksum (0x0706)
+ */
+enum ice_status ice_nvm_recalculate_checksum(struct ice_hw *hw)
+{
+       struct ice_aqc_nvm_checksum *cmd;
+       struct ice_aq_desc desc;
+       enum ice_status status;
+
+       status = ice_acquire_nvm(hw, ICE_RES_READ);
+       if (status)
+               return status;
+
+       cmd = &desc.params.nvm_checksum;
+
+       ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum);
+       cmd->flags = ICE_AQC_NVM_CHECKSUM_RECALC;
+
+       status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
+
+       ice_release_nvm(hw);
+
+       return status;
+}
+
 /**
  * ice_nvm_access_get_features - Return the NVM access features structure
  * @cmd: NVM access command to process
@@ -1143,6 +1205,7 @@ ice_validate_nvm_rw_reg(struct ice_nvm_access_cmd *cmd)
        case GLGEN_CSR_DEBUG_C:
        case GLGEN_RSTAT:
        case GLPCI_LBARCTRL:
+       case GL_MNG_DEF_DEVID:
        case GLNVM_GENS:
        case GLNVM_FLA:
        case PF_FUNC_RID:
@@ -1151,11 +1214,11 @@ ice_validate_nvm_rw_reg(struct ice_nvm_access_cmd *cmd)
                break;
        }
 
-       for (i = 0; i <= ICE_NVM_ACCESS_GL_HIDA_MAX; i++)
+       for (i = 0; i <= GL_HIDA_MAX_INDEX; i++)
                if (offset == (u32)GL_HIDA(i))
                        return ICE_SUCCESS;
 
-       for (i = 0; i <= ICE_NVM_ACCESS_GL_HIBA_MAX; i++)
+       for (i = 0; i <= GL_HIBA_MAX_INDEX; i++)
                if (offset == (u32)GL_HIBA(i))
                        return ICE_SUCCESS;