/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2020 Intel Corporation
+ * Copyright(c) 2001-2021 Intel Corporation
*/
#include "ice_common.h"
+#define GL_MNG_DEF_DEVID 0x000B611C
+
/**
* ice_aq_read_nvm
* @hw: pointer to the HW struct
return status;
}
+/**
+ * ice_nvm_recalculate_checksum
+ * @hw: pointer to the HW struct
+ *
+ * Recalculate NVM PFA checksum (0x0706)
+ */
+enum ice_status ice_nvm_recalculate_checksum(struct ice_hw *hw)
+{
+ struct ice_aqc_nvm_checksum *cmd;
+ struct ice_aq_desc desc;
+ enum ice_status status;
+
+ status = ice_acquire_nvm(hw, ICE_RES_READ);
+ if (status)
+ return status;
+
+ cmd = &desc.params.nvm_checksum;
+
+ ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum);
+ cmd->flags = ICE_AQC_NVM_CHECKSUM_RECALC;
+
+ status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
+
+ ice_release_nvm(hw);
+
+ return status;
+}
+
/**
* ice_nvm_access_get_features - Return the NVM access features structure
* @cmd: NVM access command to process
case GLGEN_CSR_DEBUG_C:
case GLGEN_RSTAT:
case GLPCI_LBARCTRL:
+ case GL_MNG_DEF_DEVID:
case GLNVM_GENS:
case GLNVM_FLA:
case PF_FUNC_RID:
break;
}
- for (i = 0; i <= ICE_NVM_ACCESS_GL_HIDA_MAX; i++)
+ for (i = 0; i <= GL_HIDA_MAX_INDEX; i++)
if (offset == (u32)GL_HIDA(i))
return ICE_SUCCESS;
- for (i = 0; i <= ICE_NVM_ACCESS_GL_HIBA_MAX; i++)
+ for (i = 0; i <= GL_HIBA_MAX_INDEX; i++)
if (offset == (u32)GL_HIBA(i))
return ICE_SUCCESS;