ice_release_res(hw, ICE_NVM_RES_ID);
}
+/**
+ * ice_read_flash_module - Read a word from one of the main NVM modules
+ * @hw: pointer to the HW structure
+ * @bank: which bank of the module to read
+ * @module: the module to read
+ * @offset: the offset into the module in words
+ * @data: storage for the word read from the flash
+ *
+ * Read a word from the specified bank of the module. The bank must be either
+ * the 1st or 2nd bank. The word will be read using flat NVM access, and
+ * relies on the hw->flash.banks data being setup by
+ * ice_determine_active_flash_banks() during initialization.
+ */
+static enum ice_status
+ice_read_flash_module(struct ice_hw *hw, enum ice_flash_bank bank, u16 module,
+ u32 offset, u16 *data)
+{
+ struct ice_bank_info *banks = &hw->flash.banks;
+ u32 bytes = sizeof(u16);
+ enum ice_status status;
+ __le16 data_local;
+ bool second_bank;
+ u32 start;
+
+ ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
+
+ switch (bank) {
+ case ICE_1ST_FLASH_BANK:
+ second_bank = false;
+ break;
+ case ICE_2ND_FLASH_BANK:
+ second_bank = true;
+ break;
+ case ICE_INVALID_FLASH_BANK:
+ default:
+ ice_debug(hw, ICE_DBG_NVM, "Unexpected flash bank %u\n", bank);
+ return ICE_ERR_PARAM;
+ }
+
+ switch (module) {
+ case ICE_SR_1ST_NVM_BANK_PTR:
+ start = banks->nvm_ptr + (second_bank ? banks->nvm_size : 0);
+ break;
+ case ICE_SR_1ST_OROM_BANK_PTR:
+ start = banks->orom_ptr + (second_bank ? banks->orom_size : 0);
+ break;
+ case ICE_SR_NETLIST_BANK_PTR:
+ start = banks->netlist_ptr + (second_bank ? banks->netlist_size : 0);
+ break;
+ default:
+ ice_debug(hw, ICE_DBG_NVM, "Unexpected flash module 0x%04x\n", module);
+ return ICE_ERR_PARAM;
+ }
+
+ status = ice_acquire_nvm(hw, ICE_RES_READ);
+ if (status)
+ return status;
+
+ status = ice_read_flat_nvm(hw, start + offset * sizeof(u16), &bytes,
+ (_FORCE_ u8 *)&data_local, false);
+ if (!status)
+ *data = LE16_TO_CPU(data_local);
+
+ ice_release_nvm(hw);
+
+ return status;
+}
+
+/**
+ * ice_read_active_nvm_module - Read from the active main NVM module
+ * @hw: pointer to the HW structure
+ * @offset: offset into the NVM module to read, in words
+ * @data: storage for returned word value
+ *
+ * Read the specified word from the active NVM module. This includes the CSS
+ * header at the start of the NVM module.
+ */
+static enum ice_status
+ice_read_active_nvm_module(struct ice_hw *hw, u32 offset, u16 *data)
+{
+ return ice_read_flash_module(hw, hw->flash.banks.nvm_bank,
+ ICE_SR_1ST_NVM_BANK_PTR, offset, data);
+}
+
+/**
+ * ice_read_active_orom_module - Read from the active Option ROM module
+ * @hw: pointer to the HW structure
+ * @offset: offset into the OROM module to read, in words
+ * @data: storage for returned word value
+ *
+ * Read the specified word from the active Option ROM module of the flash.
+ * Note that unlike the NVM module, the CSS data is stored at the end of the
+ * module instead of at the beginning.
+ */
+static enum ice_status
+ice_read_active_orom_module(struct ice_hw *hw, u32 offset, u16 *data)
+{
+ return ice_read_flash_module(hw, hw->flash.banks.orom_bank,
+ ICE_SR_1ST_OROM_BANK_PTR, offset, data);
+}
+
/**
* ice_read_sr_word - Reads Shadow RAM word and acquire NVM if necessary
* @hw: pointer to the HW structure
return status;
}
+/**
+ * ice_get_nvm_srev - Read the security revision from the NVM CSS header
+ * @hw: pointer to the HW struct
+ * @srev: storage for security revision
+ *
+ * Read the security revision out of the CSS header of the active NVM module
+ * bank.
+ */
+static enum ice_status ice_get_nvm_srev(struct ice_hw *hw, u32 *srev)
+{
+ enum ice_status status;
+ u16 srev_l, srev_h;
+
+ status = ice_read_active_nvm_module(hw, ICE_NVM_CSS_SREV_L, &srev_l);
+ if (status)
+ return status;
+
+ status = ice_read_active_nvm_module(hw, ICE_NVM_CSS_SREV_H, &srev_h);
+ if (status)
+ return status;
+
+ *srev = srev_h << 16 | srev_l;
+
+ return ICE_SUCCESS;
+}
+
/**
* ice_get_nvm_ver_info - Read NVM version information
* @hw: pointer to the HW struct
nvm->eetrack = (eetrack_hi << 16) | eetrack_lo;
+ status = ice_get_nvm_srev(hw, &nvm->srev);
+ if (status)
+ ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM security revision.\n");
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_get_orom_srev - Read the security revision from the OROM CSS header
+ * @hw: pointer to the HW struct
+ * @srev: storage for security revision
+ *
+ * Read the security revision out of the CSS header of the active OROM module
+ * bank.
+ */
+static enum ice_status ice_get_orom_srev(struct ice_hw *hw, u32 *srev)
+{
+ enum ice_status status;
+ u16 srev_l, srev_h;
+ u32 css_start;
+
+ if (hw->flash.banks.orom_size < ICE_NVM_OROM_TRAILER_LENGTH) {
+ ice_debug(hw, ICE_DBG_NVM, "Unexpected Option ROM Size of %u\n",
+ hw->flash.banks.orom_size);
+ return ICE_ERR_CFG;
+ }
+
+ /* calculate how far into the Option ROM the CSS header starts. Note
+ * that ice_read_active_orom_module takes a word offset so we need to
+ * divide by 2 here.
+ */
+ css_start = (hw->flash.banks.orom_size - ICE_NVM_OROM_TRAILER_LENGTH) / 2;
+
+ status = ice_read_active_orom_module(hw, css_start + ICE_NVM_CSS_SREV_L, &srev_l);
+ if (status)
+ return status;
+
+ status = ice_read_active_orom_module(hw, css_start + ICE_NVM_CSS_SREV_H, &srev_h);
+ if (status)
+ return status;
+
+ *srev = srev_h << 16 | srev_l;
+
return ICE_SUCCESS;
}
orom->build = (u16)((combo_ver & ICE_OROM_VER_BUILD_MASK) >>
ICE_OROM_VER_BUILD_SHIFT);
+ status = ice_get_orom_srev(hw, &orom->srev);
+ if (status)
+ ice_debug(hw, ICE_DBG_NVM, "Failed to read Option ROM security revision.\n");
+
return ICE_SUCCESS;
}
return status;
}
+/**
+ * ice_read_sr_pointer - Read the value of a Shadow RAM pointer word
+ * @hw: pointer to the HW structure
+ * @offset: the word offset of the Shadow RAM word to read
+ * @pointer: pointer value read from Shadow RAM
+ *
+ * Read the given Shadow RAM word, and convert it to a pointer value specified
+ * in bytes. This function assumes the specified offset is a valid pointer
+ * word.
+ *
+ * Each pointer word specifies whether it is stored in word size or 4KB
+ * sector size by using the highest bit. The reported pointer value will be in
+ * bytes, intended for flat NVM reads.
+ */
+static enum ice_status
+ice_read_sr_pointer(struct ice_hw *hw, u16 offset, u32 *pointer)
+{
+ enum ice_status status;
+ u16 value;
+
+ status = ice_read_sr_word(hw, offset, &value);
+ if (status)
+ return status;
+
+ /* Determine if the pointer is in 4KB or word units */
+ if (value & ICE_SR_NVM_PTR_4KB_UNITS)
+ *pointer = (value & ~ICE_SR_NVM_PTR_4KB_UNITS) * 4 * 1024;
+ else
+ *pointer = value * 2;
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_read_sr_area_size - Read an area size from a Shadow RAM word
+ * @hw: pointer to the HW structure
+ * @offset: the word offset of the Shadow RAM to read
+ * @size: size value read from the Shadow RAM
+ *
+ * Read the given Shadow RAM word, and convert it to an area size value
+ * specified in bytes. This function assumes the specified offset is a valid
+ * area size word.
+ *
+ * Each area size word is specified in 4KB sector units. This function reports
+ * the size in bytes, intended for flat NVM reads.
+ */
+static enum ice_status
+ice_read_sr_area_size(struct ice_hw *hw, u16 offset, u32 *size)
+{
+ enum ice_status status;
+ u16 value;
+
+ status = ice_read_sr_word(hw, offset, &value);
+ if (status)
+ return status;
+
+ /* Area sizes are always specified in 4KB units */
+ *size = value * 4 * 1024;
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_determine_active_flash_banks - Discover active bank for each module
+ * @hw: pointer to the HW struct
+ *
+ * Read the Shadow RAM control word and determine which banks are active for
+ * the NVM, OROM, and Netlist modules. Also read and calculate the associated
+ * pointer and size. These values are then cached into the ice_flash_info
+ * structure for later use in order to calculate the correct offset to read
+ * from the active module.
+ */
+static enum ice_status
+ice_determine_active_flash_banks(struct ice_hw *hw)
+{
+ struct ice_bank_info *banks = &hw->flash.banks;
+ enum ice_status status;
+ u16 ctrl_word;
+
+ status = ice_read_sr_word(hw, ICE_SR_NVM_CTRL_WORD, &ctrl_word);
+ if (status) {
+ ice_debug(hw, ICE_DBG_NVM, "Failed to read the Shadow RAM control word\n");
+ return status;
+ }
+
+ /* Check that the control word indicates validity */
+ if ((ctrl_word & ICE_SR_CTRL_WORD_1_M) >> ICE_SR_CTRL_WORD_1_S != ICE_SR_CTRL_WORD_VALID) {
+ ice_debug(hw, ICE_DBG_NVM, "Shadow RAM control word is invalid\n");
+ return ICE_ERR_CFG;
+ }
+
+ if (!(ctrl_word & ICE_SR_CTRL_WORD_NVM_BANK))
+ banks->nvm_bank = ICE_1ST_FLASH_BANK;
+ else
+ banks->nvm_bank = ICE_2ND_FLASH_BANK;
+
+ if (!(ctrl_word & ICE_SR_CTRL_WORD_OROM_BANK))
+ banks->orom_bank = ICE_1ST_FLASH_BANK;
+ else
+ banks->orom_bank = ICE_2ND_FLASH_BANK;
+
+ if (!(ctrl_word & ICE_SR_CTRL_WORD_NETLIST_BANK))
+ banks->netlist_bank = ICE_1ST_FLASH_BANK;
+ else
+ banks->netlist_bank = ICE_2ND_FLASH_BANK;
+
+ status = ice_read_sr_pointer(hw, ICE_SR_1ST_NVM_BANK_PTR, &banks->nvm_ptr);
+ if (status) {
+ ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank pointer\n");
+ return status;
+ }
+
+ status = ice_read_sr_area_size(hw, ICE_SR_NVM_BANK_SIZE, &banks->nvm_size);
+ if (status) {
+ ice_debug(hw, ICE_DBG_NVM, "Failed to read NVM bank area size\n");
+ return status;
+ }
+
+ status = ice_read_sr_pointer(hw, ICE_SR_1ST_OROM_BANK_PTR, &banks->orom_ptr);
+ if (status) {
+ ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank pointer\n");
+ return status;
+ }
+
+ status = ice_read_sr_area_size(hw, ICE_SR_OROM_BANK_SIZE, &banks->orom_size);
+ if (status) {
+ ice_debug(hw, ICE_DBG_NVM, "Failed to read OROM bank area size\n");
+ return status;
+ }
+
+ status = ice_read_sr_pointer(hw, ICE_SR_NETLIST_BANK_PTR, &banks->netlist_ptr);
+ if (status) {
+ ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank pointer\n");
+ return status;
+ }
+
+ status = ice_read_sr_area_size(hw, ICE_SR_NETLIST_BANK_SIZE, &banks->netlist_size);
+ if (status) {
+ ice_debug(hw, ICE_DBG_NVM, "Failed to read Netlist bank area size\n");
+ return status;
+ }
+
+ return ICE_SUCCESS;
+}
+
/**
* ice_init_nvm - initializes NVM setting
* @hw: pointer to the HW struct
return status;
}
+ status = ice_determine_active_flash_banks(hw);
+ if (status) {
+ ice_debug(hw, ICE_DBG_NVM, "Failed to determine active flash banks.\n");
+ return status;
+ }
+
status = ice_get_nvm_ver_info(hw, &flash->nvm);
if (status) {
ice_debug(hw, ICE_DBG_INIT, "Failed to read NVM info.\n");
git.droids-corp.org / dpdk.git / blobdiff