/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2018-2020 Intel Corporation
+ * Copyright(c) 2018-2021 Intel Corporation
*/
#ifndef _ICE_OSDEP_H_
#include <rte_cycles.h>
#include <rte_spinlock.h>
#include <rte_log.h>
-#include <rte_random.h>
#include <rte_io.h>
#include "ice_alloc.h"
#define __be64 uint64_t
#endif
+/* Avoid macro redefinition warning on Windows */
+#ifdef RTE_EXEC_ENV_WINDOWS
+#ifdef min
+#undef min
+#endif
+#ifdef max
+#undef max
+#endif
+#endif
#define min(a, b) RTE_MIN(a, b)
#define max(a, b) RTE_MAX(a, b)
#endif
#define ICE_PCI_REG_WRITE(reg, value) writel(value, reg)
+#define ICE_PCI_REG_WC_WRITE(reg, value) rte_write32_wc(value, reg)
#define ICE_READ_REG(hw, reg) rd32(hw, reg)
#define ICE_WRITE_REG(hw, reg, value) wr32(hw, reg, value)
} __rte_packed;
#define ice_malloc(h, s) rte_zmalloc(NULL, s, 0)
-#define ice_calloc(h, c, s) rte_zmalloc(NULL, (c) * (s), 0)
+#define ice_calloc(h, c, s) rte_calloc(NULL, c, s, 0)
#define ice_free(h, m) rte_free(m)
#define ice_memset(a, b, c, d) memset((a), (b), (c))
ice_alloc_dma_mem(__rte_unused struct ice_hw *hw,
struct ice_dma_mem *mem, u64 size)
{
+ static uint64_t ice_dma_memzone_id;
const struct rte_memzone *mz = NULL;
char z_name[RTE_MEMZONE_NAMESIZE];
if (!mem)
return NULL;
- snprintf(z_name, sizeof(z_name), "ice_dma_%"PRIu64, rte_rand());
+ snprintf(z_name, sizeof(z_name), "ice_dma_%" PRIu64,
+ __atomic_fetch_add(&ice_dma_memzone_id, 1, __ATOMIC_RELAXED));
mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
0, RTE_PGSIZE_2M);
if (!mz)