/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2018-2020 Intel Corporation
+ * Copyright(c) 2018-2021 Intel Corporation
*/
#ifndef _ICE_OSDEP_H_
#define __be64 uint64_t
#endif
+/* Avoid macro redefinition warning on Windows */
+#ifdef RTE_EXEC_ENV_WINDOWS
+#ifdef min
+#undef min
+#endif
+#ifdef max
+#undef max
+#endif
+#endif
#define min(a, b) RTE_MIN(a, b)
#define max(a, b) RTE_MAX(a, b)
+#ifdef RTE_EXEC_ENV_WINDOWS
+#define ice_access _access
+#else
+#define ice_access access
+#endif
+
#define FIELD_SIZEOF(t, f) RTE_SIZEOF_FIELD(t, f)
#define ARRAY_SIZE(arr) RTE_DIM(arr)
#endif
#define ICE_PCI_REG_WRITE(reg, value) writel(value, reg)
+#define ICE_PCI_REG_WC_WRITE(reg, value) rte_write32_wc(value, reg)
#define ICE_READ_REG(hw, reg) rd32(hw, reg)
#define ICE_WRITE_REG(hw, reg, value) wr32(hw, reg, value)
} __rte_packed;
#define ice_malloc(h, s) rte_zmalloc(NULL, s, 0)
-#define ice_calloc(h, c, s) rte_zmalloc(NULL, (c) * (s), 0)
+#define ice_calloc(h, c, s) rte_calloc(NULL, c, s, 0)
#define ice_free(h, m) rte_free(m)
#define ice_memset(a, b, c, d) memset((a), (b), (c))