net/ice/base: cache NVM module bank information

[dpdk.git] / drivers / net / ice / base / ice_type.h

diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 997f97e..1e1c672 100644 (file)
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -511,14 +511,42 @@ struct ice_orom_info {
        u16 build;                      /* Build version of OROM */
 };
 
-/* NVM Information */
+/* NVM version information */
 struct ice_nvm_info {
+       u32 eetrack;
+       u8 major;
+       u8 minor;
+};
+
+/* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules
+ * of the flash image.
+ */
+enum ice_flash_bank {
+       ICE_INVALID_FLASH_BANK,
+       ICE_1ST_FLASH_BANK,
+       ICE_2ND_FLASH_BANK,
+};
+
+/* information for accessing NVM, OROM, and Netlist flash banks */
+struct ice_bank_info {
+       u32 nvm_ptr;                            /* Pointer to 1st NVM bank */
+       u32 nvm_size;                           /* Size of NVM bank */
+       u32 orom_ptr;                           /* Pointer to 1st OROM bank */
+       u32 orom_size;                          /* Size of OROM bank */
+       u32 netlist_ptr;                        /* Pointer to 1st Netlist bank */
+       u32 netlist_size;                       /* Size of Netlist bank */
+       enum ice_flash_bank nvm_bank;           /* Active NVM bank */
+       enum ice_flash_bank orom_bank;          /* Active OROM bank */
+       enum ice_flash_bank netlist_bank;       /* Active Netlist bank */
+};
+
+/* Flash Chip Information */
+struct ice_flash_info {
        struct ice_orom_info orom;      /* Option ROM version info */
-       u32 eetrack;                    /* NVM data version */
+       struct ice_nvm_info nvm;        /* NVM version information */
+       struct ice_bank_info banks;     /* Flash Bank information */
        u16 sr_words;                   /* Shadow RAM size in words */
        u32 flash_size;                 /* Size of available flash in bytes */
-       u8 major_ver;                   /* major version of dev starter */
-       u8 minor_ver;                   /* minor version of dev starter */
        u8 blank_nvm_mode;              /* is NVM empty (no FW present) */
 };
 
@@ -753,6 +781,14 @@ struct ice_dcbx_cfg {
 #define ICE_DCBX_APPS_NON_WILLING      0x1
 };
 
+struct ice_qos_cfg {
+       struct ice_dcbx_cfg local_dcbx_cfg;     /* Oper/Local Cfg */
+       struct ice_dcbx_cfg desired_dcbx_cfg;   /* CEE Desired Cfg */
+       struct ice_dcbx_cfg remote_dcbx_cfg;    /* Peer Cfg */
+       u8 dcbx_status : 3;                     /* see ICE_DCBX_STATUS_DIS */
+       u8 is_sw_lldp : 1;
+};
+
 struct ice_port_info {
        struct ice_sched_node *root;    /* Root Node per Port */
        struct ice_hw *hw;              /* back pointer to HW instance */
@@ -774,17 +810,9 @@ struct ice_port_info {
        struct ice_lock sched_lock;     /* protect access to TXSched tree */
        struct ice_sched_node *
                sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
-       /* List contain profile ID(s) and other params per layer */
-       struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
        struct ice_bw_type_info root_node_bw_t_info;
        struct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];
-       struct ice_dcbx_cfg local_dcbx_cfg;     /* Oper/Local Cfg */
-       /* DCBX info */
-       struct ice_dcbx_cfg remote_dcbx_cfg;    /* Peer Cfg */
-       struct ice_dcbx_cfg desired_dcbx_cfg;   /* CEE Desired Cfg */
-       /* LLDP/DCBX Status */
-       u8 dcbx_status:3;               /* see ICE_DCBX_STATUS_DIS */
-       u8 is_sw_lldp:1;
+       struct ice_qos_cfg qos_cfg;
        u8 is_vf:1;
 };
 
@@ -792,6 +820,7 @@ struct ice_switch_info {
        struct LIST_HEAD_TYPE vsi_list_map_head;
        struct ice_sw_recipe *recp_list;
        u16 prof_res_bm_init;
+       u16 max_used_prof_index;
 
        ice_declare_bitmap(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS);
 };
@@ -831,11 +860,13 @@ struct ice_hw {
        u8 sw_entry_point_layer;
        u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
        struct LIST_HEAD_TYPE agg_list; /* lists all aggregator */
+       /* List contain profile ID(s) and other params per layer */
+       struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
        struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
        u8 evb_veb;             /* true for VEB, false for VEPA */
        u8 reset_ongoing;       /* true if HW is in reset, false otherwise */
        struct ice_bus_info bus;
-       struct ice_nvm_info nvm;
+       struct ice_flash_info flash;
        struct ice_hw_dev_caps dev_caps;        /* device capabilities */
        struct ice_hw_func_caps func_caps;      /* function capabilities */
 
@@ -1091,6 +1122,12 @@ enum ice_sw_fwd_act_type {
 #define ICE_SR_PCIE_ALT_SIZE_WORDS     512
 #define ICE_SR_CTRL_WORD_1_S           0x06
 #define ICE_SR_CTRL_WORD_1_M           (0x03 << ICE_SR_CTRL_WORD_1_S)
+#define ICE_SR_CTRL_WORD_VALID         0x1
+#define ICE_SR_CTRL_WORD_OROM_BANK     BIT(3)
+#define ICE_SR_CTRL_WORD_NETLIST_BANK  BIT(4)
+#define ICE_SR_CTRL_WORD_NVM_BANK      BIT(5)
+
+#define ICE_SR_NVM_PTR_4KB_UNITS       BIT(15)
 
 /* Shadow RAM related */
 #define ICE_SR_SECTOR_SIZE_IN_WORDS    0x800