net/ice/base: add dedicate MAC type for E810

[dpdk.git] / drivers / net / ice / base / ice_type.h

diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 9773a54..3e24bb1 100644 (file)
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -34,6 +34,9 @@
 
 #define IS_ASCII(_ch)  ((_ch) < 0x80)
 
+#define ice_struct_size(ptr, field, num) \
+       (sizeof(*(ptr)) + sizeof(*(ptr)->field) * (num))
+
 #include "ice_status.h"
 #include "ice_hw_autogen.h"
 #include "ice_devids.h"
@@ -165,6 +168,7 @@ enum ice_fc_mode {
        ICE_FC_RX_PAUSE,
        ICE_FC_TX_PAUSE,
        ICE_FC_FULL,
+       ICE_FC_AUTO,
        ICE_FC_PFC,
        ICE_FC_DFLT
 };
@@ -201,6 +205,7 @@ enum ice_set_fc_aq_failures {
 /* MAC types */
 enum ice_mac_type {
        ICE_MAC_UNKNOWN = 0,
+       ICE_MAC_E810,
        ICE_MAC_GENERIC,
 };
 
@@ -480,6 +485,28 @@ struct ice_nvm_info {
        u8 blank_nvm_mode;              /* is NVM empty (no FW present)*/
 };
 
+struct ice_link_default_override_tlv {
+       u8 options;
+#define ICE_LINK_OVERRIDE_OPT_M                0x3F
+#define ICE_LINK_OVERRIDE_STRICT_MODE  BIT(0)
+#define ICE_LINK_OVERRIDE_EPCT_DIS     BIT(1)
+#define ICE_LINK_OVERRIDE_PORT_DIS     BIT(2)
+#define ICE_LINK_OVERRIDE_EN           BIT(3)
+#define ICE_LINK_OVERRIDE_AUTO_LINK_DIS        BIT(4)
+#define ICE_LINK_OVERRIDE_EEE_EN       BIT(5)
+       u8 phy_config;
+#define ICE_LINK_OVERRIDE_PHY_CFG_S    8
+#define ICE_LINK_OVERRIDE_PHY_CFG_M    (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S)
+#define ICE_LINK_OVERRIDE_PAUSE_M      0x3
+#define ICE_LINK_OVERRIDE_LESM_EN      BIT(6)
+#define ICE_LINK_OVERRIDE_AUTO_FEC_EN  BIT(7)
+       u8 fec_options;
+#define ICE_LINK_OVERRIDE_FEC_OPT_M    0xFF
+       u8 rsvd1;
+       u64 phy_type_low;
+       u64 phy_type_high;
+};
+
 #define ICE_NVM_VER_LEN        32
 
 /* Max number of port to queue branches w.r.t topology */
@@ -524,7 +551,7 @@ struct ice_sched_node {
 #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \
        LE16_TO_CPU((x)->info.eir_bw.bw_alloc)
 
-struct ice_sched_rl_profle {
+struct ice_sched_rl_profile {
        u32 rate; /* In Kbps */
        struct ice_aqc_rl_profile_elem info;
 };
@@ -741,6 +768,8 @@ struct ice_hw {
        struct ice_sched_rl_profile **cir_profiles;
        struct ice_sched_rl_profile **eir_profiles;
        struct ice_sched_rl_profile **srl_profiles;
+       /* PSM clock frequency for calculating RL profile params */
+       u32 psm_clk_freq;
        u64 debug_mask;         /* BITMAP for debug mask */
        enum ice_mac_type mac_type;
 
@@ -998,6 +1027,7 @@ enum ice_sw_fwd_act_type {
 #define ICE_SR_EMP_SR_SETTINGS_PTR             0x48
 #define ICE_SR_CONFIGURATION_METADATA_PTR      0x4D
 #define ICE_SR_IMMEDIATE_VALUES_PTR            0x4E
+#define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR       0x134
 #define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR      0x118
 
 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
@@ -1015,6 +1045,16 @@ enum ice_sw_fwd_act_type {
  */
 #define ICE_SR_SW_CHECKSUM_BASE                0xBABA
 
+/* Link override related */
+#define ICE_SR_PFA_LINK_OVERRIDE_WORDS         10
+#define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS     4
+#define ICE_SR_PFA_LINK_OVERRIDE_OFFSET                2
+#define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET    1
+#define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET    2
+#define ICE_FW_API_LINK_OVERRIDE_MAJ           1
+#define ICE_FW_API_LINK_OVERRIDE_MIN           5
+#define ICE_FW_API_LINK_OVERRIDE_PATCH         2
+
 #define ICE_PBA_FLAG_DFLT              0xFAFA
 /* Hash redirection LUT for VSI - maximum array size */
 #define ICE_VSIQF_HLUT_ARRAY_SIZE      ((VSIQF_HLUT_MAX_INDEX + 1) * 4)