ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6,
ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_UDP,
ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_DW_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_DW,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_DW_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_DW_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_DW_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_DW_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_DW_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_DW_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_DW_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_DW,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_DW_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_DW_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_DW_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_DW_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_DW_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_DW_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV4_GTPU_EH_UP_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_UP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_UP_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_UP_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_UP_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_UP_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_UP_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV4_GRE_IPV6_GTPU_EH_UP_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV4_GTPU_EH_UP_IPV6_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_UP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_UP_IPV4,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_UP_IPV4_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_UP_IPV4_TCP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_UP_IPV6,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_UP_IPV6_UDP,
+ ICE_FLTR_PTYPE_NONF_IPV6_GRE_IPV6_GTPU_EH_UP_IPV6_TCP,
ICE_FLTR_PTYPE_NONF_IPV6_UDP,
ICE_FLTR_PTYPE_NONF_IPV6_TCP,
ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
#define ICE_NVM_MGMT_SEC_REV_DISABLED BIT(0)
#define ICE_NVM_MGMT_UPDATE_DISABLED BIT(1)
#define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
+ /* PCIe reset avoidance */
+ bool pcie_reset_avoidance; /* false: not supported, true: supported */
+ /* Post update reset restriction */
+ bool reset_restrict_support; /* false: not supported, true: supported */
/* External topology device images within the NVM */
#define ICE_EXT_TOPO_DEV_IMG_COUNT 4