#define BITS_PER_BYTE 8
+#ifndef _FORCE_
+#define _FORCE_
+#endif
+
#define ICE_BYTES_PER_WORD 2
#define ICE_BYTES_PER_DWORD 4
#define ICE_MAX_TRAFFIC_CLASS 8
-#ifndef MIN_T
#define MIN_T(_t, _a, _b) min((_t)(_a), (_t)(_b))
-#endif
-#ifndef IS_ASCII
-#define IS_ASCII(_ch) ((_ch) < 0x80)
-#endif
+#define IS_ASCII(_ch) ((_ch) < 0x80)
#include "ice_status.h"
#include "ice_hw_autogen.h"
return ice_is_bit_set(&bitmap, tc);
}
-#ifndef DIV_64BIT
#define DIV_64BIT(n, d) ((n) / (d))
-#endif /* DIV_64BIT */
static inline u64 round_up_64bit(u64 a, u32 b)
{
#define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
/* debug masks - set these bits in hw->debug_mask to control output */
+#define ICE_DBG_TRACE BIT_ULL(0) /* for function-trace only */
#define ICE_DBG_INIT BIT_ULL(1)
#define ICE_DBG_RELEASE BIT_ULL(2)
-
+#define ICE_DBG_FW_LOG BIT_ULL(3)
#define ICE_DBG_LINK BIT_ULL(4)
#define ICE_DBG_PHY BIT_ULL(5)
#define ICE_DBG_QCTX BIT_ULL(6)
#define ICE_DBG_USER BIT_ULL(31)
#define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL
+#ifndef __ALWAYS_UNUSED
+#define __ALWAYS_UNUSED
+#endif
ICE_FC_DFLT
};
+enum ice_phy_cache_mode {
+ ICE_FC_MODE = 0,
+ ICE_SPEED_MODE,
+ ICE_FEC_MODE
+};
+
enum ice_fec_mode {
ICE_FEC_NONE = 0,
ICE_FEC_RS,
ICE_FEC_AUTO
};
+struct ice_phy_cache_mode_data {
+ union {
+ enum ice_fec_mode curr_user_fec_req;
+ enum ice_fc_mode curr_user_fc_req;
+ u16 curr_user_speed_req;
+ } data;
+};
+
enum ice_set_fc_aq_failures {
ICE_SET_FC_AQ_FAIL_NONE = 0,
ICE_SET_FC_AQ_FAIL_GET,
enum ice_vsi_type {
ICE_VSI_PF = 0,
ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
-#ifdef ADQ_SUPPORT
- ICE_VSI_CHNL = 4,
-#endif /* ADQ_SUPPORT */
+ ICE_VSI_LB = 6,
};
struct ice_link_status {
u64 phy_type_high;
enum ice_media_type media_type;
u8 get_link_info;
+ /* Please refer to struct ice_aqc_get_link_status_data to get
+ * detail of enable bit in curr_user_speed_req
+ */
+ u16 curr_user_speed_req;
+ enum ice_fec_mode curr_user_fec_req;
+ enum ice_fc_mode curr_user_fc_req;
+ struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
};
#define ICE_MAX_NUM_MIRROR_RULES 64
ICE_FLTR_PTYPE_MAX,
};
-/* 6 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL + 4 ICE_VSI_CHNL */
-#define ICE_MAX_FDIR_VSI_PER_FILTER 6
+/* 2 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL */
+#define ICE_MAX_FDIR_VSI_PER_FILTER 2
struct ice_fd_hw_prof {
struct ice_flow_seg_info *fdir_seg;
u32 shared_bw;
};
+/* VSI queue context structure for given TC */
+struct ice_q_ctx {
+ u16 q_handle;
+ u32 q_teid;
+ /* bw_t_info saves queue BW information */
+ struct ice_bw_type_info bw_t_info;
+};
+
/* VSI type list entry to locate corresponding VSI/aggregator nodes */
struct ice_sched_vsi_info {
struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
u8 port_state;
#define ICE_SCHED_PORT_STATE_INIT 0x0
#define ICE_SCHED_PORT_STATE_READY 0x1
+ u8 lport;
+#define ICE_LPORT_MASK 0xff
u16 dflt_tx_vsi_rule_id;
u16 dflt_tx_vsi_num;
u16 dflt_rx_vsi_rule_id;
struct ice_mac_info mac;
struct ice_phy_info phy;
struct ice_lock sched_lock; /* protect access to TXSched tree */
+ struct ice_sched_node *
+ sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
/* List contain profile ID(s) and other params per layer */
struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
/* LLDP/DCBX Status */
- u8 dcbx_status;
- u8 is_sw_lldp;
- u8 lport;
-#define ICE_LPORT_MASK 0xff
- u8 is_vf;
+ u8 dcbx_status:3; /* see ICE_DCBX_STATUS_DIS */
+ u8 is_sw_lldp:1;
+ u8 is_vf:1;
};
struct ice_switch_info {
#define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S)
#define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S)
#define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S)
+#define ICE_FW_LOG_EVNT_ALL (ICE_FW_LOG_EVNT_INFO | ICE_FW_LOG_EVNT_INIT | \
+ ICE_FW_LOG_EVNT_FLOW | ICE_FW_LOG_EVNT_ERR)
struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX];
};
u8 pf_id; /* device profile info */
u16 max_burst_size; /* driver sets this value */
+
/* Tx Scheduler values */
u16 num_tx_sched_layers;
u16 num_tx_sched_phys_layers;
u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
struct ice_fd_hw_prof **fdir_prof;
+ ice_declare_bitmap(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
+ struct ice_lock rss_locks; /* protect RSS configuration */
+ struct LIST_HEAD_TYPE rss_list_head;
};
/* Statistics collected by each port, VSI, VEB, and S-channel */
/* flow director stats */
u32 fd_sb_status;
u64 fd_sb_match;
-#ifdef ADQ_SUPPORT
- u64 ch_atr_match;
-#endif /* ADQ_SUPPORT */
};
enum ice_sw_fwd_act_type {
#define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D
#define ICE_SR_MNG_CFG_PTR 0x0E
#define ICE_SR_EMP_MODULE_PTR 0x0F
-#define ICE_SR_PBA_FLAGS 0x15
#define ICE_SR_PBA_BLOCK_PTR 0x16
#define ICE_SR_BOOT_CFG_PTR 0x17
#define ICE_SR_NVM_WOL_CFG 0x19
#define ICE_SR_NVM_BANK_SIZE 0x43
#define ICE_SR_1ND_OROM_BANK_PTR 0x44
#define ICE_SR_OROM_BANK_SIZE 0x45
+#define ICE_SR_NETLIST_BANK_PTR 0x46
+#define ICE_SR_NETLIST_BANK_SIZE 0x47
#define ICE_SR_EMP_SR_SETTINGS_PTR 0x48
#define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D
#define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E
+#define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR 0x118
/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
#define ICE_SR_VPD_SIZE_WORDS 512
git.droids-corp.org / dpdk.git / blobdiff