#define BITS_PER_BYTE 8
+#ifndef _FORCE_
+#define _FORCE_
+#endif
+
#define ICE_BYTES_PER_WORD 2
#define ICE_BYTES_PER_DWORD 4
#define ICE_MAX_TRAFFIC_CLASS 8
-#ifndef MIN_T
#define MIN_T(_t, _a, _b) min((_t)(_a), (_t)(_b))
-#endif
-#ifndef IS_ASCII
-#define IS_ASCII(_ch) ((_ch) < 0x80)
-#endif
+#define IS_ASCII(_ch) ((_ch) < 0x80)
#include "ice_status.h"
#include "ice_hw_autogen.h"
return ice_is_bit_set(&bitmap, tc);
}
-#ifndef DIV_64BIT
#define DIV_64BIT(n, d) ((n) / (d))
-#endif /* DIV_64BIT */
static inline u64 round_up_64bit(u64 a, u32 b)
{
#define ICE_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF))
/* debug masks - set these bits in hw->debug_mask to control output */
+#define ICE_DBG_TRACE BIT_ULL(0) /* for function-trace only */
#define ICE_DBG_INIT BIT_ULL(1)
#define ICE_DBG_RELEASE BIT_ULL(2)
#define ICE_DBG_FW_LOG BIT_ULL(3)
#define ICE_DBG_USER BIT_ULL(31)
#define ICE_DBG_ALL 0xFFFFFFFFFFFFFFFFULL
+#ifndef __ALWAYS_UNUSED
+#define __ALWAYS_UNUSED
+#endif
enum ice_vsi_type {
ICE_VSI_PF = 0,
ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
-#ifdef ADQ_SUPPORT
- ICE_VSI_CHNL = 4,
-#endif /* ADQ_SUPPORT */
+ ICE_VSI_LB = 6,
};
struct ice_link_status {
#define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S)
#define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S)
#define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S)
+#define ICE_FW_LOG_EVNT_ALL (ICE_FW_LOG_EVNT_INFO | ICE_FW_LOG_EVNT_INIT | \
+ ICE_FW_LOG_EVNT_FLOW | ICE_FW_LOG_EVNT_ERR)
struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX];
};
u8 pf_id; /* device profile info */
u16 max_burst_size; /* driver sets this value */
+
/* Tx Scheduler values */
u16 num_tx_sched_layers;
u16 num_tx_sched_phys_layers;
/* flow director stats */
u32 fd_sb_status;
u64 fd_sb_match;
-#ifdef ADQ_SUPPORT
- u64 ch_atr_match;
-#endif /* ADQ_SUPPORT */
};
enum ice_sw_fwd_act_type {
#define ICE_SR_CSR_PROTECTED_LIST_PTR 0x0D
#define ICE_SR_MNG_CFG_PTR 0x0E
#define ICE_SR_EMP_MODULE_PTR 0x0F
-#define ICE_SR_PBA_FLAGS 0x15
#define ICE_SR_PBA_BLOCK_PTR 0x16
#define ICE_SR_BOOT_CFG_PTR 0x17
#define ICE_SR_NVM_WOL_CFG 0x19
#define ICE_SR_NVM_BANK_SIZE 0x43
#define ICE_SR_1ND_OROM_BANK_PTR 0x44
#define ICE_SR_OROM_BANK_SIZE 0x45
+#define ICE_SR_NETLIST_BANK_PTR 0x46
+#define ICE_SR_NETLIST_BANK_SIZE 0x47
#define ICE_SR_EMP_SR_SETTINGS_PTR 0x48
#define ICE_SR_CONFIGURATION_METADATA_PTR 0x4D
#define ICE_SR_IMMEDIATE_VALUES_PTR 0x4E
+#define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR 0x118
/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
#define ICE_SR_VPD_SIZE_WORDS 512