net/ice/base: check RSS flow profile list

[dpdk.git] / drivers / net / ice / base / ice_type.h

diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index ef0b5bb..ca88931 100644 (file)
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -14,6 +14,10 @@
 
 #define BITS_PER_BYTE  8
 
+#ifndef _FORCE_
+#define _FORCE_
+#endif
+
 #define ICE_BYTES_PER_WORD     2
 #define ICE_BYTES_PER_DWORD    4
 #define ICE_MAX_TRAFFIC_CLASS  8
@@ -22,10 +26,15 @@
 #define MIN_T(_t, _a, _b)      min((_t)(_a), (_t)(_b))
 #endif
 
+#ifndef IS_ASCII
+#define IS_ASCII(_ch)  ((_ch) < 0x80)
+#endif
+
 #include "ice_status.h"
 #include "ice_hw_autogen.h"
 #include "ice_devids.h"
 #include "ice_osdep.h"
+#include "ice_bitops.h" /* Must come before ice_controlq.h */
 #include "ice_controlq.h"
 #include "ice_lan_tx_rx.h"
 #include "ice_flex_type.h"
@@ -65,7 +74,7 @@ static inline u32 ice_round_to_num(u32 N, u32 R)
 /* debug masks - set these bits in hw->debug_mask to control output */
 #define ICE_DBG_INIT           BIT_ULL(1)
 #define ICE_DBG_RELEASE                BIT_ULL(2)
-
+#define ICE_DBG_FW_LOG         BIT_ULL(3)
 #define ICE_DBG_LINK           BIT_ULL(4)
 #define ICE_DBG_PHY            BIT_ULL(5)
 #define ICE_DBG_QCTX           BIT_ULL(6)
@@ -131,6 +140,12 @@ enum ice_fc_mode {
        ICE_FC_DFLT
 };
 
+enum ice_phy_cache_mode {
+       ICE_FC_MODE = 0,
+       ICE_SPEED_MODE,
+       ICE_FEC_MODE
+};
+
 enum ice_fec_mode {
        ICE_FEC_NONE = 0,
        ICE_FEC_RS,
@@ -138,6 +153,14 @@ enum ice_fec_mode {
        ICE_FEC_AUTO
 };
 
+struct ice_phy_cache_mode_data {
+       union {
+               enum ice_fec_mode curr_user_fec_req;
+               enum ice_fc_mode curr_user_fc_req;
+               u16 curr_user_speed_req;
+       } data;
+};
+
 enum ice_set_fc_aq_failures {
        ICE_SET_FC_AQ_FAIL_NONE = 0,
        ICE_SET_FC_AQ_FAIL_GET,
@@ -215,6 +238,13 @@ struct ice_phy_info {
        u64 phy_type_high;
        enum ice_media_type media_type;
        u8 get_link_info;
+       /* Please refer to struct ice_aqc_get_link_status_data to get
+        * detail of enable bit in curr_user_speed_req
+        */
+       u16 curr_user_speed_req;
+       enum ice_fec_mode curr_user_fec_req;
+       enum ice_fc_mode curr_user_fc_req;
+       struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
 };
 
 #define ICE_MAX_NUM_MIRROR_RULES       64
@@ -235,8 +265,8 @@ enum ice_fltr_ptype {
        ICE_FLTR_PTYPE_MAX,
 };
 
-/* 6 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL + 4 ICE_VSI_CHNL */
-#define ICE_MAX_FDIR_VSI_PER_FILTER    6
+/* 2 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL */
+#define ICE_MAX_FDIR_VSI_PER_FILTER    2
 
 struct ice_fd_hw_prof {
        struct ice_flow_seg_info *fdir_seg;
@@ -552,6 +582,14 @@ struct ice_bw_type_info {
        u32 shared_bw;
 };
 
+/* VSI queue context structure for given TC */
+struct ice_q_ctx {
+       u16  q_handle;
+       u32  q_teid;
+       /* bw_t_info saves queue BW information */
+       struct ice_bw_type_info bw_t_info;
+};
+
 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
 struct ice_sched_vsi_info {
        struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
@@ -623,6 +661,8 @@ struct ice_port_info {
        u8 port_state;
 #define ICE_SCHED_PORT_STATE_INIT      0x0
 #define ICE_SCHED_PORT_STATE_READY     0x1
+       u8 lport;
+#define ICE_LPORT_MASK                 0xff
        u16 dflt_tx_vsi_rule_id;
        u16 dflt_tx_vsi_num;
        u16 dflt_rx_vsi_rule_id;
@@ -631,6 +671,8 @@ struct ice_port_info {
        struct ice_mac_info mac;
        struct ice_phy_info phy;
        struct ice_lock sched_lock;     /* protect access to TXSched tree */
+       struct ice_sched_node *
+               sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
        /* List contain profile ID(s) and other params per layer */
        struct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
        struct ice_dcbx_cfg local_dcbx_cfg;     /* Oper/Local Cfg */
@@ -638,11 +680,9 @@ struct ice_port_info {
        struct ice_dcbx_cfg remote_dcbx_cfg;    /* Peer Cfg */
        struct ice_dcbx_cfg desired_dcbx_cfg;   /* CEE Desired Cfg */
        /* LLDP/DCBX Status */
-       u8 dcbx_status;
-       u8 is_sw_lldp;
-       u8 lport;
-#define ICE_LPORT_MASK         0xff
-       u8 is_vf;
+       u8 dcbx_status:3;               /* see ICE_DCBX_STATUS_DIS */
+       u8 is_sw_lldp:1;
+       u8 is_vf:1;
 };
 
 struct ice_switch_info {
@@ -692,6 +732,7 @@ struct ice_hw {
        u8 pf_id;               /* device profile info */
 
        u16 max_burst_size;     /* driver sets this value */
+
        /* Tx Scheduler values */
        u16 num_tx_sched_layers;
        u16 num_tx_sched_phys_layers;
@@ -792,6 +833,9 @@ struct ice_hw {
        u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
 
        struct ice_fd_hw_prof **fdir_prof;
+       ice_declare_bitmap(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
+       struct ice_lock rss_locks;      /* protect RSS configuration */
+       struct LIST_HEAD_TYPE rss_list_head;
 };
 
 /* Statistics collected by each port, VSI, VEB, and S-channel */