net/ice/base: fix memory allocation wrapper

[dpdk.git] / drivers / net / ice / base / ice_type.h

diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index ce232cd..ce508a0 100644 (file)
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2020 Intel Corporation
+ * Copyright(c) 2001-2021 Intel Corporation
  */
 
 #ifndef _ICE_TYPE_H_
@@ -44,9 +44,7 @@
 #define ice_struct_size(ptr, field, num) \
        (sizeof(*(ptr)) + sizeof(*(ptr)->field) * (num))
 
-#ifndef FLEX_ARRAY_SIZE
 #define FLEX_ARRAY_SIZE(_ptr, _mem, cnt) ((cnt) * sizeof(_ptr->_mem[0]))
-#endif /* FLEX_ARRAY_SIZE */
 
 #include "ice_status.h"
 #include "ice_hw_autogen.h"
@@ -248,6 +246,7 @@ struct ice_link_status {
        u16 max_frame_size;
        u16 link_speed;
        u16 req_speeds;
+       u8 link_cfg_err;
        u8 lse_ena;     /* Link Status Event notification */
        u8 link_info;
        u8 an_info;
@@ -315,6 +314,9 @@ enum ice_fltr_ptype {
        ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4,
        ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP,
        ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP,
+       ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6,
+       ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_UDP,
+       ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV6_TCP,
        ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4,
        ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_UDP,
        ICE_FLTR_PTYPE_NONF_IPV4_GTPU_EH_IPV4_TCP,
@@ -345,6 +347,7 @@ enum ice_fltr_ptype {
        ICE_FLTR_PTYPE_NONF_ECPRI_TP0,
        ICE_FLTR_PTYPE_NONF_IPV4_UDP_ECPRI_TP0,
        ICE_FLTR_PTYPE_FRAG_IPV4,
+       ICE_FLTR_PTYPE_FRAG_IPV6,
        ICE_FLTR_PTYPE_NONF_IPV6_UDP,
        ICE_FLTR_PTYPE_NONF_IPV6_TCP,
        ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
@@ -447,6 +450,19 @@ struct ice_hw_common_caps {
 #define ICE_NVM_MGMT_SEC_REV_DISABLED          BIT(0)
 #define ICE_NVM_MGMT_UPDATE_DISABLED           BIT(1)
 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT       BIT(3)
+
+       /* External topology device images within the NVM */
+#define ICE_EXT_TOPO_DEV_IMG_COUNT     4
+       u32 ext_topo_dev_img_ver_high[ICE_EXT_TOPO_DEV_IMG_COUNT];
+       u32 ext_topo_dev_img_ver_low[ICE_EXT_TOPO_DEV_IMG_COUNT];
+       u8 ext_topo_dev_img_part_num[ICE_EXT_TOPO_DEV_IMG_COUNT];
+#define ICE_EXT_TOPO_DEV_IMG_PART_NUM_S        8
+#define ICE_EXT_TOPO_DEV_IMG_PART_NUM_M        \
+               MAKEMASK(0xFF, ICE_EXT_TOPO_DEV_IMG_PART_NUM_S)
+       bool ext_topo_dev_img_load_en[ICE_EXT_TOPO_DEV_IMG_COUNT];
+#define ICE_EXT_TOPO_DEV_IMG_LOAD_EN   BIT(0)
+       bool ext_topo_dev_img_prog_en[ICE_EXT_TOPO_DEV_IMG_COUNT];
+#define ICE_EXT_TOPO_DEV_IMG_PROG_EN   BIT(1)
 };
 
 /* Function specific capabilities */
@@ -795,7 +811,8 @@ struct ice_dcb_app_priority_table {
 };
 
 #define ICE_MAX_USER_PRIORITY          8
-#define ICE_DCBX_MAX_APPS              32
+#define ICE_DCBX_MAX_APPS              64
+#define ICE_DSCP_NUM_VAL               64
 #define ICE_LLDPDU_SIZE                        1500
 #define ICE_TLV_STATUS_OPER            0x1
 #define ICE_TLV_STATUS_SYNC            0x2
@@ -815,7 +832,14 @@ struct ice_dcbx_cfg {
        struct ice_dcb_ets_cfg etscfg;
        struct ice_dcb_ets_cfg etsrec;
        struct ice_dcb_pfc_cfg pfc;
+#define ICE_QOS_MODE_VLAN      0x0
+#define ICE_QOS_MODE_DSCP      0x1
+       u8 pfc_mode;
        struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
+       /* when DSCP mapping defined by user set its bit to 1 */
+       ice_declare_bitmap(dscp_mapped, ICE_DSCP_NUM_VAL);
+       /* array holding DSCP -> UP/TC values for DSCP L3 QoS mode */
+       u8 dscp_map[ICE_DSCP_NUM_VAL];
        u8 dcbx_mode;
 #define ICE_DCBX_MODE_CEE      0x1
 #define ICE_DCBX_MODE_IEEE     0x2
@@ -988,6 +1012,8 @@ struct ice_hw {
        /* tunneling info */
        struct ice_lock tnl_lock;
        struct ice_tunnel_table tnl;
+       /* dvm boost update information */
+       struct ice_dvm_table dvm_upd;
 
        struct ice_acl_tbl *acl_tbl;
        struct ice_fd_hw_prof **acl_prof;
@@ -1012,8 +1038,8 @@ struct ice_hw {
        ice_declare_bitmap(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
        struct ice_lock rss_locks;      /* protect RSS configuration */
        struct LIST_HEAD_TYPE rss_list_head;
-       struct ice_vlan_mode_ops vlan_mode_ops;
        ice_declare_bitmap(hw_ptype, ICE_FLOW_PTYPE_MAX);
+       u8 dvm_ena;
 };
 
 /* Statistics collected by each port, VSI, VEB, and S-channel */