static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
-static int ice_vlan_tpid_set(struct rte_eth_dev *dev,
- enum rte_vlan_type vlan_type,
- uint16_t tpid);
static int ice_rss_reta_update(struct rte_eth_dev *dev,
struct rte_eth_rss_reta_entry64 *reta_conf,
uint16_t reta_size);
{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
+ { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
+ { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
+ { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
{ .vendor_id = 0, /* sentinel */ },
};
.mac_addr_remove = ice_macaddr_remove,
.vlan_filter_set = ice_vlan_filter_set,
.vlan_offload_set = ice_vlan_offload_set,
- .vlan_tpid_set = ice_vlan_tpid_set,
.reta_update = ice_rss_reta_update,
.reta_query = ice_rss_reta_query,
.rss_hash_update = ice_rss_hash_update,
ice_res_pool_destroy(&pf->msix_pool);
ice_release_vsi(pf->main_vsi);
ice_sched_cleanup_all(hw);
+ ice_free_hw_tbls(hw);
rte_free(hw->port_info);
hw->port_info = NULL;
ice_shutdown_all_ctrlq(hw);
uint16_t i, nb_q;
int ret = 0;
bool is_safe_mode = pf->adapter->is_safe_mode;
+ uint32_t reg;
rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
nb_q = dev->data->nb_rx_queues;
if (ret)
return -EINVAL;
+ /* Enable registers for symmetric_toeplitz function. */
+ reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
+ reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
+ (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
+ ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
+
/* configure RSS for IPv4 with input set IPv4 src/dst */
ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
ICE_FLOW_SEG_HDR_IPV4, 0);
struct ice_vsi *vsi = pf->main_vsi;
uint16_t nb_rxq = 0;
uint16_t nb_txq, i;
+ uint16_t max_frame_size;
int mask, ret;
/* program Tx queues' context in hardware */
pf->adapter_stopped = false;
+ /* Set the max frame size to default value*/
+ max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
+ pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
+ ICE_FRAME_SIZE_MAX;
+
+ /* Set the max frame size to HW*/
+ ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
+
return 0;
/* stop the started queues if failed to start all queues */
return 0;
}
-static int
-ice_vlan_tpid_set(struct rte_eth_dev *dev,
- enum rte_vlan_type vlan_type,
- uint16_t tpid)
-{
- struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
- uint64_t reg_r = 0, reg_w = 0;
- uint16_t reg_id = 0;
- int ret = 0;
- int qinq = dev->data->dev_conf.rxmode.offloads &
- DEV_RX_OFFLOAD_VLAN_EXTEND;
-
- switch (vlan_type) {
- case ETH_VLAN_TYPE_OUTER:
- if (qinq)
- reg_id = 3;
- else
- reg_id = 5;
- break;
- case ETH_VLAN_TYPE_INNER:
- if (qinq) {
- reg_id = 5;
- } else {
- PMD_DRV_LOG(ERR,
- "Unsupported vlan type in single vlan.");
- return -EINVAL;
- }
- break;
- default:
- PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
- return -EINVAL;
- }
- reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id));
- PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: "
- "0x%08"PRIx64"", reg_id, reg_r);
-
- reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M));
- reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S);
- if (reg_r == reg_w) {
- PMD_DRV_LOG(DEBUG, "No need to write");
- return 0;
- }
-
- ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w);
- PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
- "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
-
- return ret;
-}
-
static int
ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
{