#include "base/ice_sched.h"
#include "base/ice_flow.h"
#include "base/ice_dcb.h"
+#include "base/ice_common.h"
#include "ice_ethdev.h"
#include "ice_rxtx.h"
#include "ice_generic_flow.h"
#define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package"
#define ICE_COMMS_PKG_NAME "ICE COMMS Package"
#define ICE_MAX_PKG_FILENAME_SIZE 256
+#define ICE_MAX_RES_DESC_NUM 1024
int ice_logtype_init;
int ice_logtype_driver;
static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
-static int ice_vlan_tpid_set(struct rte_eth_dev *dev,
- enum rte_vlan_type vlan_type,
- uint16_t tpid);
static int ice_rss_reta_update(struct rte_eth_dev *dev,
struct rte_eth_rss_reta_entry64 *reta_conf,
uint16_t reta_size);
{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
+ { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
+ { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
+ { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
{ .vendor_id = 0, /* sentinel */ },
};
.mac_addr_remove = ice_macaddr_remove,
.vlan_filter_set = ice_vlan_filter_set,
.vlan_offload_set = ice_vlan_offload_set,
- .vlan_tpid_set = ice_vlan_tpid_set,
.reta_update = ice_rss_reta_update,
.reta_query = ice_rss_reta_query,
.rss_hash_update = ice_rss_hash_update,
ice_init_proto_xtr(dev);
+ if (hw->func_caps.fd_fltr_guar > 0 ||
+ hw->func_caps.fd_fltr_best_effort > 0) {
+ pf->flags |= ICE_FLAG_FDIR;
+ pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
+ pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
+ } else {
+ pf->fdir_nb_qps = 0;
+ }
+ pf->fdir_qp_offset = 0;
+
return 0;
}
-static struct ice_vsi *
+struct ice_vsi *
ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
{
struct ice_hw *hw = ICE_PF_TO_HW(pf);
struct rte_ether_addr mac_addr;
uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
uint8_t tc_bitmap = 0x1;
+ uint16_t cfg;
/* hw->num_lports = 1 in NIC mode */
vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
memset(&vsi_ctx, 0, sizeof(vsi_ctx));
- /* base_queue in used in queue mapping of VSI add/update command.
- * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ
- * cases in the first stage. Only Main VSI.
- */
- vsi->base_queue = 0;
switch (type) {
case ICE_VSI_PF:
vsi->nb_qps = pf->lan_nb_qps;
+ vsi->base_queue = 1;
ice_vsi_config_default_rss(&vsi_ctx.info);
vsi_ctx.alloc_from_pool = true;
vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
+
+ /* FDIR */
+ cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
+ ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
+ vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
+ cfg = ICE_AQ_VSI_FD_ENABLE | ICE_AQ_VSI_FD_PROG_ENABLE;
+ vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
+ vsi_ctx.info.max_fd_fltr_dedicated =
+ rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
+ vsi_ctx.info.max_fd_fltr_shared =
+ rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
+
/* Enable VLAN/UP trip */
ret = ice_vsi_config_tc_queue_mapping(vsi,
&vsi_ctx.info,
goto fail_mem;
}
+ break;
+ case ICE_VSI_CTRL:
+ vsi->nb_qps = pf->fdir_nb_qps;
+ vsi->base_queue = ICE_FDIR_QUEUE_ID;
+ vsi_ctx.alloc_from_pool = true;
+ vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
+
+ cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
+ vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
+ cfg = ICE_AQ_VSI_FD_ENABLE | ICE_AQ_VSI_FD_PROG_ENABLE;
+ vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
+ vsi_ctx.info.sw_id = hw->port_info->sw_id;
+ ret = ice_vsi_config_tc_queue_mapping(vsi,
+ &vsi_ctx.info,
+ ICE_DEFAULT_TCMAP);
+ if (ret) {
+ PMD_INIT_LOG(ERR,
+ "tc queue mapping with vsi failed, "
+ "err = %d",
+ ret);
+ goto fail_mem;
+ }
break;
default:
/* for other types of VSI */
}
vsi->msix_intr = ret;
vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
+ } else if (type == ICE_VSI_CTRL) {
+ ret = ice_res_pool_alloc(&pf->msix_pool, 1);
+ if (ret < 0) {
+ PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
+ vsi->vsi_id, ret);
+ }
+ vsi->msix_intr = ret;
+ vsi->nb_msix = 1;
} else {
vsi->msix_intr = 0;
vsi->nb_msix = 0;
pf->vsis_allocated = vsi_ctx.vsis_allocd;
pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
- /* MAC configuration */
- rte_memcpy(pf->dev_addr.addr_bytes,
- hw->port_info->mac.perm_addr,
- ETH_ADDR_LEN);
+ if (type == ICE_VSI_PF) {
+ /* MAC configuration */
+ rte_memcpy(pf->dev_addr.addr_bytes,
+ hw->port_info->mac.perm_addr,
+ ETH_ADDR_LEN);
- rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
- ret = ice_add_mac_filter(vsi, &mac_addr);
- if (ret != ICE_SUCCESS)
- PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
+ rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
+ ret = ice_add_mac_filter(vsi, &mac_addr);
+ if (ret != ICE_SUCCESS)
+ PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
- rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
- ret = ice_add_mac_filter(vsi, &mac_addr);
- if (ret != ICE_SUCCESS)
- PMD_INIT_LOG(ERR, "Failed to add MAC filter");
+ rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
+ ret = ice_add_mac_filter(vsi, &mac_addr);
+ if (ret != ICE_SUCCESS)
+ PMD_INIT_LOG(ERR, "Failed to add MAC filter");
+ }
/* At the beginning, only TC0. */
/* What we need here is the maximam number of the TX queues.
static int
ice_pf_setup(struct ice_pf *pf)
{
+ struct ice_hw *hw = ICE_PF_TO_HW(pf);
struct ice_vsi *vsi;
+ uint16_t unused;
/* Clear all stats counters */
pf->offset_loaded = FALSE;
memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
+ /* force guaranteed filter pool for PF */
+ ice_alloc_fd_guar_item(hw, &unused,
+ hw->func_caps.fd_fltr_guar);
+ /* force shared filter pool for PF */
+ ice_alloc_fd_shrd_item(hw, &unused,
+ hw->func_caps.fd_fltr_best_effort);
+
vsi = ice_setup_vsi(pf, ICE_VSI_PF);
if (!vsi) {
PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
return ret;
}
+static enum ice_status
+ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
+ uint16_t num, uint16_t desc_id,
+ uint16_t *prof_buf, uint16_t *num_prof)
+{
+ struct ice_aqc_get_allocd_res_desc_resp *resp_buf;
+ int ret;
+ uint16_t buf_len;
+ bool res_shared = 1;
+ struct ice_aq_desc aq_desc;
+ struct ice_sq_cd *cd = NULL;
+ struct ice_aqc_get_allocd_res_desc *cmd =
+ &aq_desc.params.get_res_desc;
+
+ buf_len = sizeof(resp_buf->elem) * num;
+ resp_buf = ice_malloc(hw, buf_len);
+ if (!resp_buf)
+ return -ENOMEM;
+
+ ice_fill_dflt_direct_cmd_desc(&aq_desc,
+ ice_aqc_opc_get_allocd_res_desc);
+
+ cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
+ ICE_AQC_RES_TYPE_M) | (res_shared ?
+ ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
+ cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
+
+ ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
+ if (!ret)
+ *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
+ else
+ goto exit;
+
+ ice_memcpy(prof_buf, resp_buf->elem, sizeof(resp_buf->elem) *
+ (*num_prof), ICE_NONDMA_TO_NONDMA);
+
+exit:
+ rte_free(resp_buf);
+ return ret;
+}
+static int
+ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
+{
+ int ret;
+ uint16_t prof_id;
+ uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
+ uint16_t first_desc = 1;
+ uint16_t num_prof = 0;
+
+ ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
+ first_desc, prof_buf, &num_prof);
+ if (ret) {
+ PMD_INIT_LOG(ERR, "Failed to get fxp resource");
+ return ret;
+ }
+
+ for (prof_id = 0; prof_id < num_prof; prof_id++) {
+ ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
+ if (ret) {
+ PMD_INIT_LOG(ERR, "Failed to free fxp resource");
+ return ret;
+ }
+ }
+ return 0;
+}
+
+static int
+ice_reset_fxp_resource(struct ice_hw *hw)
+{
+ int ret;
+
+ ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
+ if (ret) {
+ PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
+ return ret;
+ }
+
+ ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
+ if (ret) {
+ PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
+ return ret;
+ }
+
+ return 0;
+}
+
static int
ice_dev_init(struct rte_eth_dev *dev)
{
return ret;
}
+ ret = ice_reset_fxp_resource(hw);
+ if (ret) {
+ PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
+ return ret;
+ }
+
return 0;
err_pf_setup:
return ret;
}
-static int
+int
ice_release_vsi(struct ice_vsi *vsi)
{
struct ice_hw *hw;
/* disable all queue interrupts */
ice_vsi_disable_queues_intr(main_vsi);
+ if (pf->fdir.fdir_vsi)
+ ice_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
+
/* Clear all queues and release mbufs */
ice_clear_queues(dev);
ice_res_pool_destroy(&pf->msix_pool);
ice_release_vsi(pf->main_vsi);
ice_sched_cleanup_all(hw);
+ ice_free_hw_tbls(hw);
rte_free(hw->port_info);
hw->port_info = NULL;
ice_shutdown_all_ctrlq(hw);
uint16_t i, nb_q;
int ret = 0;
bool is_safe_mode = pf->adapter->is_safe_mode;
+ uint32_t reg;
rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
nb_q = dev->data->nb_rx_queues;
if (ret)
return -EINVAL;
+ /* Enable registers for symmetric_toeplitz function. */
+ reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
+ reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
+ (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
+ ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
+
/* configure RSS for IPv4 with input set IPv4 src/dst */
ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
ICE_FLOW_SEG_HDR_IPV4, 0);
PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
__func__, ret);
+ /* configure RSS for gtpu with input set TEID */
+ ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_GTP_U_IPV4_TEID,
+ ICE_FLOW_SEG_HDR_GTPU_IP, 0);
+ if (ret)
+ PMD_DRV_LOG(ERR, "%s GTPU_TEID rss flow fail %d",
+ __func__, ret);
+
+ /**
+ * configure RSS for pppoe/pppod with input set
+ * Source MAC and Session ID
+ */
+ ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_PPPOE_SESS_ID_ETH,
+ ICE_FLOW_SEG_HDR_PPPOE, 0);
+ if (ret)
+ PMD_DRV_LOG(ERR, "%s PPPoE/PPPoD_SessionID rss flow fail %d",
+ __func__, ret);
+
return 0;
}
/* Enable interrupts for all the queues */
ice_vsi_enable_queues_intr(vsi);
+ /* Enable FDIR MSIX interrupt */
+ if (pf->fdir.fdir_vsi) {
+ ice_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
+ ice_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
+ }
+
rte_intr_enable(intr_handle);
return 0;
struct ice_vsi *vsi = pf->main_vsi;
uint16_t nb_rxq = 0;
uint16_t nb_txq, i;
+ uint16_t max_frame_size;
int mask, ret;
/* program Tx queues' context in hardware */
pf->adapter_stopped = false;
+ /* Set the max frame size to default value*/
+ max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
+ pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
+ ICE_FRAME_SIZE_MAX;
+
+ /* Set the max frame size to HW*/
+ ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
+
return 0;
/* stop the started queues if failed to start all queues */
return 0;
}
-static int
-ice_vlan_tpid_set(struct rte_eth_dev *dev,
- enum rte_vlan_type vlan_type,
- uint16_t tpid)
-{
- struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
- uint64_t reg_r = 0, reg_w = 0;
- uint16_t reg_id = 0;
- int ret = 0;
- int qinq = dev->data->dev_conf.rxmode.offloads &
- DEV_RX_OFFLOAD_VLAN_EXTEND;
-
- switch (vlan_type) {
- case ETH_VLAN_TYPE_OUTER:
- if (qinq)
- reg_id = 3;
- else
- reg_id = 5;
- break;
- case ETH_VLAN_TYPE_INNER:
- if (qinq) {
- reg_id = 5;
- } else {
- PMD_DRV_LOG(ERR,
- "Unsupported vlan type in single vlan.");
- return -EINVAL;
- }
- break;
- default:
- PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
- return -EINVAL;
- }
- reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id));
- PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: "
- "0x%08"PRIx64"", reg_id, reg_r);
-
- reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M));
- reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S);
- if (reg_r == reg_w) {
- PMD_DRV_LOG(DEBUG, "No need to write");
- return 0;
- }
-
- ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w);
- PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
- "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
-
- return ret;
-}
-
static int
ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
{