/* devargs */
#define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
#define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support"
-#define ICE_FLOW_MARK_SUPPORT_ARG "flow-mark-support"
#define ICE_PROTO_XTR_ARG "proto_xtr"
static const char * const ice_valid_args[] = {
ICE_SAFE_MODE_SUPPORT_ARG,
ICE_PIPELINE_MODE_SUPPORT_ARG,
- ICE_FLOW_MARK_SUPPORT_ARG,
ICE_PROTO_XTR_ARG,
NULL
};
bool required;
};
+static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX];
+
static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
[PROTO_XTR_VLAN] = {
.param = { .name = "ice_dynflag_proto_xtr_vlan" },
[PROTO_XTR_TCP] = {
.param = { .name = "ice_dynflag_proto_xtr_tcp" },
.ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
+ [PROTO_XTR_IP_OFFSET] = {
+ .param = { .name = "ice_dynflag_proto_xtr_ip_offset" },
+ .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask },
};
#define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
static int ice_dev_configure(struct rte_eth_dev *dev);
static int ice_dev_start(struct rte_eth_dev *dev);
static void ice_dev_stop(struct rte_eth_dev *dev);
-static void ice_dev_close(struct rte_eth_dev *dev);
+static int ice_dev_close(struct rte_eth_dev *dev);
static int ice_dev_reset(struct rte_eth_dev *dev);
static int ice_dev_info_get(struct rte_eth_dev *dev,
struct rte_eth_dev_info *dev_info);
struct rte_eth_udp_tunnel *udp_tunnel);
static const struct rte_pci_id pci_id_ice_map[] = {
+ { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
+ { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) },
+ { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) },
+ { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) },
+ { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) },
{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) },
{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) },
- { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
- { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) },
- { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) },
- { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) },
- { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) },
+ { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_BACKPLANE) },
+ { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SFP) },
+ { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_10G_BASE_T) },
+ { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SGMII) },
{ .vendor_id = 0, /* sentinel */ },
};
.tx_burst_mode_get = ice_tx_burst_mode_get,
.get_eeprom_length = ice_get_eeprom_length,
.get_eeprom = ice_get_eeprom,
- .rx_queue_count = ice_rx_queue_count,
- .rx_descriptor_status = ice_rx_descriptor_status,
- .tx_descriptor_status = ice_tx_descriptor_status,
.stats_get = ice_stats_get,
.stats_reset = ice_stats_reset,
.xstats_get = ice_xstats_get,
{ "ipv6", PROTO_XTR_IPV6 },
{ "ipv6_flow", PROTO_XTR_IPV6_FLOW },
{ "tcp", PROTO_XTR_TCP },
+ { "ip_offset", PROTO_XTR_IP_OFFSET },
};
uint32_t i;
return 0;
}
-static bool
-ice_proto_xtr_support(struct ice_hw *hw)
+static void
+ice_check_proto_xtr_support(struct ice_hw *hw)
{
#define FLX_REG(val, fld, idx) \
(((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
static struct {
uint32_t rxdid;
- uint16_t protid_0;
- uint16_t protid_1;
+ uint8_t opcode;
+ uint8_t protid_0;
+ uint8_t protid_1;
} xtr_sets[] = {
- { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O },
- { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S,
- ICE_PROT_IPV4_OF_OR_S },
- { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S,
- ICE_PROT_IPV6_OF_OR_S },
- { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S,
- ICE_PROT_IPV6_OF_OR_S },
- { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
+ [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN,
+ ICE_RX_OPC_EXTRACT,
+ ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O},
+ [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4,
+ ICE_RX_OPC_EXTRACT,
+ ICE_PROT_IPV4_OF_OR_S,
+ ICE_PROT_IPV4_OF_OR_S },
+ [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6,
+ ICE_RX_OPC_EXTRACT,
+ ICE_PROT_IPV6_OF_OR_S,
+ ICE_PROT_IPV6_OF_OR_S },
+ [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW,
+ ICE_RX_OPC_EXTRACT,
+ ICE_PROT_IPV6_OF_OR_S,
+ ICE_PROT_IPV6_OF_OR_S },
+ [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP,
+ ICE_RX_OPC_EXTRACT,
+ ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
+ [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET,
+ ICE_RX_OPC_PROTID,
+ ICE_PROT_IPV4_OF_OR_S,
+ ICE_PROT_IPV6_OF_OR_S },
};
uint32_t i;
if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
- if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 ||
- FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT)
- return false;
+ if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 &&
+ FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode)
+ ice_proto_xtr_hw_support[i] = true;
}
if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
- if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 ||
- FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT)
- return false;
+ if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 &&
+ FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode)
+ ice_proto_xtr_hw_support[i] = true;
}
}
-
- return true;
}
static int
case ice_aqc_opc_get_link_status:
ret = ice_link_update(dev, 0);
if (!ret)
- _rte_eth_dev_callback_process
+ rte_eth_dev_callback_process
(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
break;
default:
PMD_DRV_LOG(INFO, "OICR: link state change event");
ret = ice_link_update(dev, 0);
if (!ret)
- _rte_eth_dev_callback_process
+ rte_eth_dev_callback_process
(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
}
#endif
int offset;
uint16_t i;
- if (!ice_proto_xtr_support(hw)) {
- PMD_DRV_LOG(NOTICE, "Protocol extraction is not supported");
- return;
- }
-
pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
if (unlikely(pf->proto_xtr == NULL)) {
PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
if (likely(!proto_xtr_enable))
return;
+ ice_check_proto_xtr_support(hw);
+
offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
if (unlikely(offset == -1)) {
PMD_DRV_LOG(ERR,
if (!ol_flag->required)
continue;
+ if (!ice_proto_xtr_hw_support[i]) {
+ PMD_DRV_LOG(ERR,
+ "Protocol extraction type %u is not supported in hardware",
+ i);
+ rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
+ break;
+ }
+
offset = rte_mbuf_dynflag_register(&ol_flag->param);
if (unlikely(offset == -1)) {
PMD_DRV_LOG(ERR,
return 0;
}
-/* PCIe configuration space setting */
-#define PCI_CFG_SPACE_SIZE 256
-#define PCI_CFG_SPACE_EXP_SIZE 4096
-#define PCI_EXT_CAP_ID(header) (int)((header) & 0x0000ffff)
-#define PCI_EXT_CAP_NEXT(header) (((header) >> 20) & 0xffc)
-#define PCI_EXT_CAP_ID_DSN 0x03
-
-static int
-ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
-{
- uint32_t header;
- int ttl;
- int pos = PCI_CFG_SPACE_SIZE;
-
- /* minimum 8 bytes per capability */
- ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
-
- if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
- PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
- return -1;
- }
-
- /*
- * If we have no capabilities, this is indicated by cap ID,
- * cap version and next pointer all being 0.
- */
- if (header == 0)
- return 0;
-
- while (ttl-- > 0) {
- if (PCI_EXT_CAP_ID(header) == cap)
- return pos;
-
- pos = PCI_EXT_CAP_NEXT(header);
-
- if (pos < PCI_CFG_SPACE_SIZE)
- break;
-
- if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
- PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
- return -1;
- }
- }
-
- return 0;
-}
-
/*
* Extract device serial number from PCIe Configuration Space and
* determine the pkg file path according to the DSN.
static int
ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
{
- int pos;
+ off_t pos;
char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
uint32_t dsn_low, dsn_high;
memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
- pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
+ pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN);
if (pos) {
rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
if (ret)
goto bail;
- ret = rte_kvargs_process(kvlist, ICE_FLOW_MARK_SUPPORT_ARG,
- &parse_bool, &ad->devargs.flow_mark_support);
- if (ret)
- goto bail;
-
bail:
rte_kvargs_free(kvlist);
return ret;
uint16_t num, uint16_t desc_id,
uint16_t *prof_buf, uint16_t *num_prof)
{
- struct ice_aqc_get_allocd_res_desc_resp *resp_buf;
+ struct ice_aqc_res_elem *resp_buf;
int ret;
uint16_t buf_len;
bool res_shared = 1;
struct ice_aqc_get_allocd_res_desc *cmd =
&aq_desc.params.get_res_desc;
- buf_len = sizeof(resp_buf->elem) * num;
+ buf_len = sizeof(*resp_buf) * num;
resp_buf = ice_malloc(hw, buf_len);
if (!resp_buf)
return -ENOMEM;
else
goto exit;
- ice_memcpy(prof_buf, resp_buf->elem, sizeof(resp_buf->elem) *
+ ice_memcpy(prof_buf, resp_buf, sizeof(*resp_buf) *
(*num_prof), ICE_NONDMA_TO_NONDMA);
exit:
ICE_HASH_CFG_RESET(&pf->gtpu_hash_ctx.ipv6_tcp);
}
+static uint64_t
+ice_get_supported_rxdid(struct ice_hw *hw)
+{
+ uint64_t supported_rxdid = 0; /* bitmap for supported RXDID */
+ uint32_t regval;
+ int i;
+
+ supported_rxdid |= BIT(ICE_RXDID_LEGACY_1);
+
+ for (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) {
+ regval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0));
+ if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S)
+ & GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M)
+ supported_rxdid |= BIT(i);
+ }
+ return supported_rxdid;
+}
+
static int
ice_dev_init(struct rte_eth_dev *dev)
{
int ret;
dev->dev_ops = &ice_eth_dev_ops;
+ dev->rx_queue_count = ice_rx_queue_count;
+ dev->rx_descriptor_status = ice_rx_descriptor_status;
+ dev->tx_descriptor_status = ice_tx_descriptor_status;
dev->rx_pkt_burst = ice_recv_pkts;
dev->tx_pkt_burst = ice_xmit_pkts;
dev->tx_pkt_prepare = ice_prep_pkts;
goto err_init_mac;
}
- /* Pass the information to the rte_eth_dev_close() that it should also
- * release the private port resources.
- */
- dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
-
ret = ice_res_pool_init(&pf->msix_pool, 1,
hw->func_caps.common_cap.num_msix_vectors - 1);
if (ret) {
return ret;
}
+ pf->supported_rxdid = ice_get_supported_rxdid(hw);
+
return 0;
err_pf_setup:
pf->adapter_stopped = true;
}
-static void
+static int
ice_dev_close(struct rte_eth_dev *dev)
{
struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
struct ice_adapter *ad =
ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
+ if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+ return 0;
+
/* Since stop will make link down, then the link event will be
* triggered, disable the irq firstly to avoid the port_infoe etc
* resources deallocation causing the interrupt service thread
/* unregister callback func from eal lib */
rte_intr_callback_unregister(intr_handle,
ice_interrupt_handler, dev);
+
+ return 0;
}
static int
link.link_speed = ETH_SPEED_NUM_100G;
break;
case ICE_AQ_LINK_SPEED_UNKNOWN:
- default:
PMD_DRV_LOG(ERR, "Unknown link speed");
+ link.link_speed = ETH_SPEED_NUM_UNKNOWN;
+ break;
+ default:
+ PMD_DRV_LOG(ERR, "None link speed");
link.link_speed = ETH_SPEED_NUM_NONE;
break;
}
u16 build;
int ret;
- ver = hw->nvm.orom.major;
- patch = hw->nvm.orom.patch;
- build = hw->nvm.orom.build;
+ ver = hw->flash.orom.major;
+ patch = hw->flash.orom.patch;
+ build = hw->flash.orom.build;
ret = snprintf(fw_version, fw_size,
- "%d.%d 0x%08x %d.%d.%d",
- hw->nvm.major_ver,
- hw->nvm.minor_ver,
- hw->nvm.eetrack,
+ "%x.%02x 0x%08x %d.%d.%d",
+ hw->flash.nvm.major,
+ hw->flash.nvm.minor,
+ hw->flash.nvm.eetrack,
ver, build, patch);
/* add the size of '\0' */
{
struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
- return hw->nvm.flash_size;
+ return hw->flash.flash_size;
}
static int
RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
RTE_PMD_REGISTER_PARAM_STRING(net_ice,
- ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>"
+ ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>"
ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
- ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"
- ICE_FLOW_MARK_SUPPORT_ARG "=<0|1>");
+ ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
RTE_LOG_REGISTER(ice_logtype_init, pmd.net.ice.init, NOTICE);
RTE_LOG_REGISTER(ice_logtype_driver, pmd.net.ice.driver, NOTICE);