#include "base/ice_flow.h"
#include "base/ice_dcb.h"
#include "base/ice_common.h"
+
+#include "rte_pmd_ice.h"
#include "ice_ethdev.h"
#include "ice_rxtx.h"
#include "ice_generic_flow.h"
NULL
};
+static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
+ .name = "ice_dynfield_proto_xtr_metadata",
+ .size = sizeof(uint32_t),
+ .align = __alignof__(uint32_t),
+ .flags = 0,
+};
+
+struct proto_xtr_ol_flag {
+ const struct rte_mbuf_dynflag param;
+ uint64_t *ol_flag;
+ bool required;
+};
+
+static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
+ [PROTO_XTR_VLAN] = {
+ .param = { .name = "ice_dynflag_proto_xtr_vlan" },
+ .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
+ [PROTO_XTR_IPV4] = {
+ .param = { .name = "ice_dynflag_proto_xtr_ipv4" },
+ .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
+ [PROTO_XTR_IPV6] = {
+ .param = { .name = "ice_dynflag_proto_xtr_ipv6" },
+ .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
+ [PROTO_XTR_IPV6_FLOW] = {
+ .param = { .name = "ice_dynflag_proto_xtr_ipv6_flow" },
+ .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
+ [PROTO_XTR_TCP] = {
+ .param = { .name = "ice_dynflag_proto_xtr_tcp" },
+ .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
+};
+
#define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
/* DDP package search path */
static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
-static int ice_vlan_tpid_set(struct rte_eth_dev *dev,
- enum rte_vlan_type vlan_type,
- uint16_t tpid);
static int ice_rss_reta_update(struct rte_eth_dev *dev,
struct rte_eth_rss_reta_entry64 *reta_conf,
uint16_t reta_size);
.mac_addr_remove = ice_macaddr_remove,
.vlan_filter_set = ice_vlan_filter_set,
.vlan_offload_set = ice_vlan_offload_set,
- .vlan_tpid_set = ice_vlan_tpid_set,
.reta_update = ice_rss_reta_update,
.reta_query = ice_rss_reta_query,
.rss_hash_update = ice_rss_hash_update,
ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
struct ice_hw *hw = ICE_PF_TO_HW(pf);
+ const struct proto_xtr_ol_flag *ol_flag;
+ bool proto_xtr_enable = false;
+ int offset;
uint16_t i;
if (!ice_proto_xtr_support(hw)) {
return;
}
- for (i = 0; i < pf->lan_nb_qps; i++)
+ for (i = 0; i < pf->lan_nb_qps; i++) {
pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
ad->devargs.proto_xtr[i] :
ad->devargs.proto_xtr_dflt;
+
+ if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
+ uint8_t type = pf->proto_xtr[i];
+
+ ice_proto_xtr_ol_flag_params[type].required = true;
+ proto_xtr_enable = true;
+ }
+ }
+
+ if (likely(!proto_xtr_enable))
+ return;
+
+ offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
+ if (unlikely(offset == -1)) {
+ PMD_DRV_LOG(ERR,
+ "Protocol extraction metadata is disabled in mbuf with error %d",
+ -rte_errno);
+ return;
+ }
+
+ PMD_DRV_LOG(DEBUG,
+ "Protocol extraction metadata offset in mbuf is : %d",
+ offset);
+ rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
+
+ for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
+ ol_flag = &ice_proto_xtr_ol_flag_params[i];
+
+ if (!ol_flag->required)
+ continue;
+
+ offset = rte_mbuf_dynflag_register(&ol_flag->param);
+ if (unlikely(offset == -1)) {
+ PMD_DRV_LOG(ERR,
+ "Protocol extraction offload '%s' failed to register with error %d",
+ ol_flag->param.name, -rte_errno);
+
+ rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
+ break;
+ }
+
+ PMD_DRV_LOG(DEBUG,
+ "Protocol extraction offload '%s' offset in mbuf is : %d",
+ ol_flag->param.name, offset);
+ *ol_flag->ol_flag = 1ULL << offset;
+ }
}
/* Initialize SW parameters of PF */
ice_res_pool_destroy(&pf->msix_pool);
ice_release_vsi(pf->main_vsi);
ice_sched_cleanup_all(hw);
+ ice_free_hw_tbls(hw);
rte_free(hw->port_info);
hw->port_info = NULL;
ice_shutdown_all_ctrlq(hw);
ad->rx_bulk_alloc_allowed = true;
ad->tx_simple_allowed = true;
+ dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
+
return 0;
}
DEV_RX_OFFLOAD_TCP_CKSUM |
DEV_RX_OFFLOAD_QINQ_STRIP |
DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
- DEV_RX_OFFLOAD_VLAN_EXTEND;
+ DEV_RX_OFFLOAD_VLAN_EXTEND |
+ DEV_RX_OFFLOAD_RSS_HASH;
dev_info->tx_offload_capa |=
DEV_TX_OFFLOAD_QINQ_INSERT |
DEV_TX_OFFLOAD_IPV4_CKSUM |
return 0;
}
-static int
-ice_vlan_tpid_set(struct rte_eth_dev *dev,
- enum rte_vlan_type vlan_type,
- uint16_t tpid)
-{
- struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
- uint64_t reg_r = 0, reg_w = 0;
- uint16_t reg_id = 0;
- int ret = 0;
- int qinq = dev->data->dev_conf.rxmode.offloads &
- DEV_RX_OFFLOAD_VLAN_EXTEND;
-
- switch (vlan_type) {
- case ETH_VLAN_TYPE_OUTER:
- if (qinq)
- reg_id = 3;
- else
- reg_id = 5;
- break;
- case ETH_VLAN_TYPE_INNER:
- if (qinq) {
- reg_id = 5;
- } else {
- PMD_DRV_LOG(ERR,
- "Unsupported vlan type in single vlan.");
- return -EINVAL;
- }
- break;
- default:
- PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
- return -EINVAL;
- }
- reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id));
- PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: "
- "0x%08"PRIx64"", reg_id, reg_r);
-
- reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M));
- reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S);
- if (reg_r == reg_w) {
- PMD_DRV_LOG(DEBUG, "No need to write");
- return 0;
- }
-
- ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w);
- PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
- "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
-
- return ret;
-}
-
static int
ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
{