#include <rte_kvargs.h>
+#include <rte_ethdev_driver.h>
+
#include "base/ice_common.h"
#include "base/ice_adminq_cmd.h"
ETH_RSS_NONFRAG_IPV6_OTHER | \
ETH_RSS_L2_PAYLOAD)
+/**
+ * The overhead from MTU to max frame size.
+ * Considering QinQ packet, the VLAN tag needs to be counted twice.
+ */
+#define ICE_ETH_OVERHEAD \
+ (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + ICE_VLAN_TAG_SIZE * 2)
+
+/* DDP package type */
+enum ice_pkg_type {
+ ICE_PKG_TYPE_UNKNOWN,
+ ICE_PKG_TYPE_OS_DEFAULT,
+ ICE_PKG_TYPE_COMMS,
+};
+
struct ice_adapter;
/**
* MAC filter structure
*/
struct ice_mac_filter_info {
- struct ether_addr mac_addr;
+ struct rte_ether_addr mac_addr;
};
TAILQ_HEAD(ice_mac_filter_list, ice_mac_filter);
bool offset_loaded;
};
+struct rte_flow;
+TAILQ_HEAD(ice_flow_list, rte_flow);
+
+struct ice_flow_parser_node;
+TAILQ_HEAD(ice_parser_list, ice_flow_parser_node);
+
+struct ice_fdir_filter_conf {
+ struct ice_fdir_fltr input;
+
+ struct ice_fdir_counter *counter; /* flow specific counter context */
+ struct rte_flow_action_count act_count;
+
+ uint64_t input_set;
+};
+
+#define ICE_FDIR_COUNTER_DEFAULT_POOL_SIZE 1
+#define ICE_FDIR_COUNTER_MAX_POOL_SIZE 32
+#define ICE_FDIR_COUNTERS_PER_BLOCK 256
+#define ICE_FDIR_COUNTER_INDEX(base_idx) \
+ ((base_idx) * ICE_FDIR_COUNTERS_PER_BLOCK)
+struct ice_fdir_counter_pool;
+
+struct ice_fdir_counter {
+ TAILQ_ENTRY(ice_fdir_counter) next;
+ struct ice_fdir_counter_pool *pool;
+ uint8_t shared;
+ uint32_t ref_cnt;
+ uint32_t id;
+ uint64_t hits;
+ uint64_t bytes;
+ uint32_t hw_index;
+};
+
+TAILQ_HEAD(ice_fdir_counter_list, ice_fdir_counter);
+
+struct ice_fdir_counter_pool {
+ TAILQ_ENTRY(ice_fdir_counter_pool) next;
+ struct ice_fdir_counter_list counter_list;
+ struct ice_fdir_counter counters[0];
+};
+
+TAILQ_HEAD(ice_fdir_counter_pool_list, ice_fdir_counter_pool);
+
+struct ice_fdir_counter_pool_container {
+ struct ice_fdir_counter_pool_list pool_list;
+ struct ice_fdir_counter_pool *pools[ICE_FDIR_COUNTER_MAX_POOL_SIZE];
+ uint8_t index_free;
+};
+
+/**
+ * A structure used to define fields of a FDIR related info.
+ */
+struct ice_fdir_info {
+ struct ice_vsi *fdir_vsi; /* pointer to fdir VSI structure */
+ struct ice_tx_queue *txq;
+ struct ice_rx_queue *rxq;
+ void *prg_pkt; /* memory for fdir program packet */
+ uint64_t dma_addr; /* physic address of packet memory*/
+ struct ice_fdir_filter_conf conf;
+
+ struct ice_fdir_counter_pool_container counter;
+};
+
struct ice_pf {
struct ice_adapter *adapter; /* The adapter this PF associate to */
struct ice_vsi *main_vsi; /* pointer to main VSI structure */
struct ice_res_pool_info qp_pool; /*Queue pair pool */
struct ice_res_pool_info msix_pool; /* MSIX interrupt pool */
struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
- struct ether_addr dev_addr; /* PF device mac address */
+ struct rte_ether_addr dev_addr; /* PF device mac address */
uint64_t flags; /* PF feature flags */
uint16_t hash_lut_size; /* The size of hash lookup table */
uint16_t lan_nb_qp_max;
uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
+ uint16_t base_queue; /* The base queue pairs index in the device */
+ uint8_t *proto_xtr; /* Protocol extraction type for all queues */
+ uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
+ uint16_t fdir_qp_offset;
+ struct ice_fdir_info fdir; /* flow director info */
+ uint16_t hw_prof_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX];
+ uint16_t fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX];
struct ice_hw_port_stats stats_offset;
struct ice_hw_port_stats stats;
/* internal packet statistics, it should be excluded from the total */
struct ice_eth_stats internal_stats;
bool offset_loaded;
bool adapter_stopped;
+ struct ice_flow_list flow_list;
+ struct ice_parser_list rss_parser_list;
+ struct ice_parser_list perm_parser_list;
+ struct ice_parser_list dist_parser_list;
+};
+
+#define ICE_MAX_QUEUE_NUM 2048
+
+/**
+ * Cache devargs parse result.
+ */
+struct ice_devargs {
+ int safe_mode_support;
+ uint8_t proto_xtr_dflt;
+ int pipe_mode_support;
+ uint8_t proto_xtr[ICE_MAX_QUEUE_NUM];
};
/**
struct rte_eth_dev *eth_dev;
struct ice_pf pf;
bool rx_bulk_alloc_allowed;
+ bool rx_vec_allowed;
+ bool tx_vec_allowed;
bool tx_simple_allowed;
/* ptype mapping table */
uint32_t ptype_tbl[ICE_MAX_PKT_TYPE] __rte_cache_min_aligned;
+ bool is_safe_mode;
+ struct ice_devargs devargs;
+ enum ice_pkg_type active_pkg_type; /* loaded ddp package type */
};
struct ice_vsi_vlan_pvid_info {
#define ICE_PF_TO_ETH_DEV(pf) \
(((struct ice_pf *)pf)->adapter->eth_dev)
+struct ice_vsi *
+ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type);
+int
+ice_release_vsi(struct ice_vsi *vsi);
+
static inline int
ice_align_floor(int n)
{
return 0;
return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
}
+
+#define ICE_PHY_TYPE_SUPPORT_50G(phy_type) \
+ (((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CR2) || \
+ ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR2) || \
+ ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR2) || \
+ ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR2) || \
+ ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC) || \
+ ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2) || \
+ ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC) || \
+ ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2) || \
+ ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CP) || \
+ ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR) || \
+ ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_FR) || \
+ ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR) || \
+ ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4) || \
+ ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC) || \
+ ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1))
+
+#define ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type) \
+ (((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR4) || \
+ ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR4) || \
+ ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_LR4) || \
+ ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR4) || \
+ ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC) || \
+ ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4) || \
+ ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC) || \
+ ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4) || \
+ ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4) || \
+ ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4) || \
+ ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CP2) || \
+ ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR2) || \
+ ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_DR))
+
+#define ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type) \
+ (((phy_type) & ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4) || \
+ ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC) || \
+ ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2) || \
+ ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC) || \
+ ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2))
+
#endif /* _ICE_ETHDEV_H_ */