#define _ICE_ETHDEV_H_
#include <rte_kvargs.h>
+#include <rte_time.h>
-#include <rte_ethdev_driver.h>
+#include <ethdev_driver.h>
#include "base/ice_common.h"
#include "base/ice_adminq_cmd.h"
#define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
#define ICE_MAX_PKG_FILENAME_SIZE 256
-#define MAX_ACL_ENTRIES 512
+#define MAX_ACL_NORMAL_ENTRIES 256
/**
* vlan_id is a 12 bit number.
*/
#define ICE_ETH_OVERHEAD \
(RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + ICE_VLAN_TAG_SIZE * 2)
+#define ICE_ETH_MAX_LEN (RTE_ETHER_MTU + ICE_ETH_OVERHEAD)
#define ICE_RXTX_BYTES_HIGH(bytes) ((bytes) & ~ICE_40_BIT_MASK)
#define ICE_RXTX_BYTES_LOW(bytes) ((bytes) & ICE_40_BIT_MASK)
/* Max number of flexible descriptor rxdid */
#define ICE_FLEX_DESC_RXDID_MAX_NUM 64
+/* Per-channel register definitions */
+#define GLTSYN_AUX_OUT(_chan, _idx) (GLTSYN_AUX_OUT_0(_idx) + ((_chan) * 8))
+#define GLTSYN_CLKO(_chan, _idx) (GLTSYN_CLKO_0(_idx) + ((_chan) * 8))
+#define GLTSYN_TGT_L(_chan, _idx) (GLTSYN_TGT_L_0(_idx) + ((_chan) * 16))
+#define GLTSYN_TGT_H(_chan, _idx) (GLTSYN_TGT_H_0(_idx) + ((_chan) * 16))
+
/* DDP package type */
enum ice_pkg_type {
ICE_PKG_TYPE_UNKNOWN,
ICE_PKG_TYPE_COMMS,
};
+enum pps_type {
+ PPS_NONE,
+ PPS_PIN,
+ PPS_MAX,
+};
+
struct ice_adapter;
/**
struct ice_mac_filter_info mac_info;
};
+struct ice_vlan {
+ uint16_t tpid;
+ uint16_t vid;
+};
+
+#define ICE_VLAN(tpid, vid) \
+ ((struct ice_vlan){ tpid, vid })
+
/**
* VLAN filter structure
*/
struct ice_vlan_filter_info {
- uint16_t vlan_id;
+ struct ice_vlan vlan;
};
TAILQ_HEAD(ice_vlan_filter_list, ice_vlan_filter);
struct ice_fdir_counter *counter; /* flow specific counter context */
struct rte_flow_action_count act_count;
- uint64_t input_set;
- uint64_t outer_input_set; /* only for tunnel packets outer fields */
+ uint64_t input_set_o; /* used for non-tunnel or tunnel outer fields */
+ uint64_t input_set_i; /* only for tunnel inner fields */
uint32_t mark_flag;
};
struct ice_acl_info {
struct ice_acl_conf conf;
struct rte_bitmap *slots;
- uint64_t hw_entry_id[MAX_ACL_ENTRIES];
+ uint64_t hw_entry_id[MAX_ACL_NORMAL_ENTRIES];
};
struct ice_pf {
};
#define ICE_MAX_QUEUE_NUM 2048
+#define ICE_MAX_PIN_NUM 4
/**
* Cache devargs parse result.
*/
struct ice_devargs {
+ int rx_low_latency;
int safe_mode_support;
uint8_t proto_xtr_dflt;
int pipe_mode_support;
uint8_t proto_xtr[ICE_MAX_QUEUE_NUM];
+ uint8_t pin_idx;
+ uint8_t pps_out_ena;
};
/**
struct ice_adapter {
/* Common for both PF and VF */
struct ice_hw hw;
- struct rte_eth_dev *eth_dev;
struct ice_pf pf;
bool rx_bulk_alloc_allowed;
bool rx_vec_allowed;
struct ice_devargs devargs;
enum ice_pkg_type active_pkg_type; /* loaded ddp package type */
uint16_t fdir_ref_cnt;
+ /* For PTP */
+ struct rte_timecounter systime_tc;
+ struct rte_timecounter rx_tstamp_tc;
+ struct rte_timecounter tx_tstamp_tc;
+ bool ptp_ena;
+#ifdef RTE_ARCH_X86
+ bool rx_use_avx2;
+ bool rx_use_avx512;
+ bool tx_use_avx2;
+ bool tx_use_avx512;
+#endif
};
struct ice_vsi_vlan_pvid_info {
(&(((struct ice_vsi *)vsi)->adapter->hw))
#define ICE_VSI_TO_PF(vsi) \
(&(((struct ice_vsi *)vsi)->adapter->pf))
-#define ICE_VSI_TO_ETH_DEV(vsi) \
- (((struct ice_vsi *)vsi)->adapter->eth_dev)
/* ICE_PF_TO */
#define ICE_PF_TO_HW(pf) \
#define ICE_PF_TO_ETH_DEV(pf) \
(((struct ice_pf *)pf)->adapter->eth_dev)
-enum ice_pkg_type ice_load_pkg_type(struct ice_hw *hw);
+int
+ice_load_pkg(struct ice_adapter *adapter, bool use_dsn, uint64_t dsn);
struct ice_vsi *
ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type);
int