#include <rte_kvargs.h>
-#include <rte_ethdev_driver.h>
+#include <ethdev_driver.h>
#include "base/ice_common.h"
#include "base/ice_adminq_cmd.h"
+#include "base/ice_flow.h"
#define ICE_VLAN_TAG_SIZE 4
#define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
#define ICE_MAX_PKG_FILENAME_SIZE 256
+#define MAX_ACL_ENTRIES 512
+
/**
* vlan_id is a 12 bit number.
* The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
*/
#define ICE_ETH_OVERHEAD \
(RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + ICE_VLAN_TAG_SIZE * 2)
+#define ICE_ETH_MAX_LEN (RTE_ETHER_MTU + ICE_ETH_OVERHEAD)
#define ICE_RXTX_BYTES_HIGH(bytes) ((bytes) & ~ICE_40_BIT_MASK)
#define ICE_RXTX_BYTES_LOW(bytes) ((bytes) & ICE_40_BIT_MASK)
#define ICE_HASH_GTPU_CTX_DW_IP_TCP 8
#define ICE_HASH_GTPU_CTX_MAX 9
-enum ice_rss_hash_func {
- ICE_RSS_HASH_TOEPLITZ = 0,
- ICE_RSS_HASH_TOEPLITZ_SYMMETRIC = 1,
- ICE_RSS_HASH_XOR = 2,
- ICE_RSS_HASH_JHASH = 3,
-};
-
-struct ice_rss_hash_cfg {
- u32 addl_hdrs;
- u64 hash_flds;
- enum ice_rss_hash_func hash_func;
-};
-
struct ice_hash_gtpu_ctx {
struct ice_rss_hash_cfg ctx[ICE_HASH_GTPU_CTX_MAX];
};
struct ice_hash_gtpu_ctx gtpu6;
};
+struct ice_acl_conf {
+ struct ice_fdir_fltr input;
+ uint64_t input_set;
+};
+
+/**
+ * A structure used to define fields of ACL related info.
+ */
+struct ice_acl_info {
+ struct ice_acl_conf conf;
+ struct rte_bitmap *slots;
+ uint64_t hw_entry_id[MAX_ACL_ENTRIES];
+};
+
struct ice_pf {
struct ice_adapter *adapter; /* The adapter this PF associate to */
struct ice_vsi *main_vsi; /* pointer to main VSI structure */
uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
uint16_t fdir_qp_offset;
struct ice_fdir_info fdir; /* flow director info */
+ struct ice_acl_info acl; /* ACL info */
struct ice_hash_ctx hash_ctx;
uint16_t hw_prof_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX];
uint16_t fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX];
uint64_t old_rx_bytes;
uint64_t old_tx_bytes;
uint64_t supported_rxdid; /* bitmap for supported RXDID */
+ uint64_t rss_hf;
};
#define ICE_MAX_QUEUE_NUM 2048
void ice_vsi_disable_queues_intr(struct ice_vsi *vsi);
void ice_vsi_queues_bind_intr(struct ice_vsi *vsi);
int ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
- uint64_t hash_fld, uint32_t pkt_hdr, bool symm);
+ struct ice_rss_hash_cfg *cfg);
int ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
- uint64_t hash_fld, uint32_t pkt_hdr);
+ struct ice_rss_hash_cfg *cfg);
static inline int
ice_align_floor(int n)