#include "base/ice_common.h"
#include "base/ice_adminq_cmd.h"
+#include "base/ice_flow.h"
#define ICE_VLAN_TAG_SIZE 4
#define ICE_MAX_PKT_TYPE 1024
+/* DDP package search path */
+#define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
+#define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
+#define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
+#define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
+#define ICE_MAX_PKG_FILENAME_SIZE 256
+
+#define MAX_ACL_ENTRIES 512
+
/**
* vlan_id is a 12 bit number.
* The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
ICE_FLAG_VF_MAC_BY_PF)
#define ICE_RSS_OFFLOAD_ALL ( \
+ ETH_RSS_IPV4 | \
ETH_RSS_FRAG_IPV4 | \
ETH_RSS_NONFRAG_IPV4_TCP | \
ETH_RSS_NONFRAG_IPV4_UDP | \
ETH_RSS_NONFRAG_IPV4_SCTP | \
ETH_RSS_NONFRAG_IPV4_OTHER | \
+ ETH_RSS_IPV6 | \
ETH_RSS_FRAG_IPV6 | \
ETH_RSS_NONFRAG_IPV6_TCP | \
ETH_RSS_NONFRAG_IPV6_UDP | \
#define ICE_ETH_OVERHEAD \
(RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + ICE_VLAN_TAG_SIZE * 2)
+#define ICE_RXTX_BYTES_HIGH(bytes) ((bytes) & ~ICE_40_BIT_MASK)
+#define ICE_RXTX_BYTES_LOW(bytes) ((bytes) & ICE_40_BIT_MASK)
+
+/* Max number of flexible descriptor rxdid */
+#define ICE_FLEX_DESC_RXDID_MAX_NUM 64
+
/* DDP package type */
enum ice_pkg_type {
ICE_PKG_TYPE_UNKNOWN,
struct ice_eth_stats eth_stats_offset;
struct ice_eth_stats eth_stats;
bool offset_loaded;
+ uint64_t old_rx_bytes;
+ uint64_t old_tx_bytes;
+};
+
+enum proto_xtr_type {
+ PROTO_XTR_NONE,
+ PROTO_XTR_VLAN,
+ PROTO_XTR_IPV4,
+ PROTO_XTR_IPV6,
+ PROTO_XTR_IPV6_FLOW,
+ PROTO_XTR_TCP,
+ PROTO_XTR_IP_OFFSET,
+ PROTO_XTR_MAX /* The last one */
+};
+
+enum ice_fdir_tunnel_type {
+ ICE_FDIR_TUNNEL_TYPE_NONE = 0,
+ ICE_FDIR_TUNNEL_TYPE_VXLAN,
+ ICE_FDIR_TUNNEL_TYPE_GTPU,
+ ICE_FDIR_TUNNEL_TYPE_GTPU_EH,
};
struct rte_flow;
struct ice_flow_parser_node;
TAILQ_HEAD(ice_parser_list, ice_flow_parser_node);
+struct ice_fdir_filter_conf {
+ struct ice_fdir_fltr input;
+ enum ice_fdir_tunnel_type tunnel_type;
+
+ struct ice_fdir_counter *counter; /* flow specific counter context */
+ struct rte_flow_action_count act_count;
+
+ uint64_t input_set;
+ uint64_t outer_input_set; /* only for tunnel packets outer fields */
+ uint32_t mark_flag;
+};
+
+#define ICE_MAX_FDIR_FILTER_NUM (1024 * 16)
+
+struct ice_fdir_fltr_pattern {
+ enum ice_fltr_ptype flow_type;
+
+ union {
+ struct ice_fdir_v4 v4;
+ struct ice_fdir_v6 v6;
+ } ip, mask;
+
+ struct ice_fdir_udp_gtp gtpu_data;
+ struct ice_fdir_udp_gtp gtpu_mask;
+
+ struct ice_fdir_extra ext_data;
+ struct ice_fdir_extra ext_mask;
+
+ enum ice_fdir_tunnel_type tunnel_type;
+};
+
+#define ICE_FDIR_COUNTER_DEFAULT_POOL_SIZE 1
+#define ICE_FDIR_COUNTER_MAX_POOL_SIZE 32
+#define ICE_FDIR_COUNTERS_PER_BLOCK 256
+#define ICE_FDIR_COUNTER_INDEX(base_idx) \
+ ((base_idx) * ICE_FDIR_COUNTERS_PER_BLOCK)
+struct ice_fdir_counter_pool;
+
+struct ice_fdir_counter {
+ TAILQ_ENTRY(ice_fdir_counter) next;
+ struct ice_fdir_counter_pool *pool;
+ uint8_t shared;
+ uint32_t ref_cnt;
+ uint32_t id;
+ uint64_t hits;
+ uint64_t bytes;
+ uint32_t hw_index;
+};
+
+TAILQ_HEAD(ice_fdir_counter_list, ice_fdir_counter);
+
+struct ice_fdir_counter_pool {
+ TAILQ_ENTRY(ice_fdir_counter_pool) next;
+ struct ice_fdir_counter_list counter_list;
+ struct ice_fdir_counter counters[0];
+};
+
+TAILQ_HEAD(ice_fdir_counter_pool_list, ice_fdir_counter_pool);
+
+struct ice_fdir_counter_pool_container {
+ struct ice_fdir_counter_pool_list pool_list;
+ struct ice_fdir_counter_pool *pools[ICE_FDIR_COUNTER_MAX_POOL_SIZE];
+ uint8_t index_free;
+};
+
/**
* A structure used to define fields of a FDIR related info.
*/
struct ice_rx_queue *rxq;
void *prg_pkt; /* memory for fdir program packet */
uint64_t dma_addr; /* physic address of packet memory*/
+ const struct rte_memzone *mz;
+ struct ice_fdir_filter_conf conf;
+
+ struct ice_fdir_filter_conf **hash_map;
+ struct rte_hash *hash_table;
+
+ struct ice_fdir_counter_pool_container counter;
+};
+
+#define ICE_HASH_GTPU_CTX_EH_IP 0
+#define ICE_HASH_GTPU_CTX_EH_IP_UDP 1
+#define ICE_HASH_GTPU_CTX_EH_IP_TCP 2
+#define ICE_HASH_GTPU_CTX_UP_IP 3
+#define ICE_HASH_GTPU_CTX_UP_IP_UDP 4
+#define ICE_HASH_GTPU_CTX_UP_IP_TCP 5
+#define ICE_HASH_GTPU_CTX_DW_IP 6
+#define ICE_HASH_GTPU_CTX_DW_IP_UDP 7
+#define ICE_HASH_GTPU_CTX_DW_IP_TCP 8
+#define ICE_HASH_GTPU_CTX_MAX 9
+
+struct ice_hash_gtpu_ctx {
+ struct ice_rss_hash_cfg ctx[ICE_HASH_GTPU_CTX_MAX];
+};
+
+struct ice_hash_ctx {
+ struct ice_hash_gtpu_ctx gtpu4;
+ struct ice_hash_gtpu_ctx gtpu6;
+};
+
+struct ice_acl_conf {
+ struct ice_fdir_fltr input;
+ uint64_t input_set;
+};
+
+/**
+ * A structure used to define fields of ACL related info.
+ */
+struct ice_acl_info {
+ struct ice_acl_conf conf;
+ struct rte_bitmap *slots;
+ uint64_t hw_entry_id[MAX_ACL_ENTRIES];
};
struct ice_pf {
uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
uint16_t fdir_qp_offset;
struct ice_fdir_info fdir; /* flow director info */
+ struct ice_acl_info acl; /* ACL info */
+ struct ice_hash_ctx hash_ctx;
+ uint16_t hw_prof_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX];
+ uint16_t fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX];
struct ice_hw_port_stats stats_offset;
struct ice_hw_port_stats stats;
/* internal packet statistics, it should be excluded from the total */
bool offset_loaded;
bool adapter_stopped;
struct ice_flow_list flow_list;
+ rte_spinlock_t flow_ops_lock;
struct ice_parser_list rss_parser_list;
struct ice_parser_list perm_parser_list;
struct ice_parser_list dist_parser_list;
+ bool init_link_up;
+ uint64_t old_rx_bytes;
+ uint64_t old_tx_bytes;
+ uint64_t supported_rxdid; /* bitmap for supported RXDID */
+ uint64_t rss_hf;
};
#define ICE_MAX_QUEUE_NUM 2048
bool is_safe_mode;
struct ice_devargs devargs;
enum ice_pkg_type active_pkg_type; /* loaded ddp package type */
+ uint16_t fdir_ref_cnt;
};
struct ice_vsi_vlan_pvid_info {
#define ICE_PF_TO_ETH_DEV(pf) \
(((struct ice_pf *)pf)->adapter->eth_dev)
+enum ice_pkg_type ice_load_pkg_type(struct ice_hw *hw);
struct ice_vsi *
ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type);
int
ice_release_vsi(struct ice_vsi *vsi);
+void ice_vsi_enable_queues_intr(struct ice_vsi *vsi);
+void ice_vsi_disable_queues_intr(struct ice_vsi *vsi);
+void ice_vsi_queues_bind_intr(struct ice_vsi *vsi);
+int ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
+ struct ice_rss_hash_cfg *cfg);
+int ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
+ struct ice_rss_hash_cfg *cfg);
static inline int
ice_align_floor(int n)
git.droids-corp.org / dpdk.git / blobdiff