#define ICE_PPP_IPV4_PROTO 0x0021
#define ICE_PPP_IPV6_PROTO 0x0057
#define ICE_IPV4_PROTO_NVGRE 0x002F
+#define ICE_SW_PRI_BASE 6
#define ICE_SW_INSET_ETHER ( \
ICE_INSET_DMAC | ICE_INSET_SMAC | ICE_INSET_ETHERTYPE)
ICE_INSET_IPV4_PROTO | ICE_INSET_IPV4_TTL | ICE_INSET_IPV4_TOS)
#define ICE_SW_INSET_MAC_QINQ_IPV4 ( \
ICE_SW_INSET_MAC_QINQ | ICE_SW_INSET_MAC_IPV4)
+#define ICE_SW_INSET_MAC_QINQ_IPV4_TCP ( \
+ ICE_SW_INSET_MAC_QINQ_IPV4 | \
+ ICE_INSET_TCP_DST_PORT | ICE_INSET_TCP_SRC_PORT)
+#define ICE_SW_INSET_MAC_QINQ_IPV4_UDP ( \
+ ICE_SW_INSET_MAC_QINQ_IPV4 | \
+ ICE_INSET_UDP_DST_PORT | ICE_INSET_UDP_SRC_PORT)
#define ICE_SW_INSET_MAC_IPV4_TCP ( \
ICE_INSET_DMAC | ICE_INSET_IPV4_DST | ICE_INSET_IPV4_SRC | \
ICE_INSET_IPV4_TTL | ICE_INSET_IPV4_TOS | \
ICE_INSET_IPV6_NEXT_HDR)
#define ICE_SW_INSET_MAC_QINQ_IPV6 ( \
ICE_SW_INSET_MAC_QINQ | ICE_SW_INSET_MAC_IPV6)
+#define ICE_SW_INSET_MAC_QINQ_IPV6_TCP ( \
+ ICE_SW_INSET_MAC_QINQ_IPV6 | \
+ ICE_INSET_TCP_DST_PORT | ICE_INSET_TCP_SRC_PORT)
+#define ICE_SW_INSET_MAC_QINQ_IPV6_UDP ( \
+ ICE_SW_INSET_MAC_QINQ_IPV6 | \
+ ICE_INSET_UDP_DST_PORT | ICE_INSET_UDP_SRC_PORT)
#define ICE_SW_INSET_MAC_IPV6_TCP ( \
ICE_INSET_DMAC | ICE_INSET_IPV6_DST | ICE_INSET_IPV6_SRC | \
ICE_INSET_IPV6_HOP_LIMIT | ICE_INSET_IPV6_TC | \
{pattern_eth_ipv4_pfcp, ICE_INSET_NONE, ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_ipv6_pfcp, ICE_INSET_NONE, ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_qinq_ipv4, ICE_SW_INSET_MAC_QINQ_IPV4, ICE_INSET_NONE, ICE_INSET_NONE},
+ {pattern_eth_qinq_ipv4_tcp, ICE_SW_INSET_MAC_QINQ_IPV4_TCP, ICE_INSET_NONE, ICE_INSET_NONE},
+ {pattern_eth_qinq_ipv4_udp, ICE_SW_INSET_MAC_QINQ_IPV4_UDP, ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_qinq_ipv6, ICE_SW_INSET_MAC_QINQ_IPV6, ICE_INSET_NONE, ICE_INSET_NONE},
+ {pattern_eth_qinq_ipv6_tcp, ICE_SW_INSET_MAC_QINQ_IPV6_TCP, ICE_INSET_NONE, ICE_INSET_NONE},
+ {pattern_eth_qinq_ipv6_udp, ICE_SW_INSET_MAC_QINQ_IPV6_UDP, ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_qinq_pppoes, ICE_SW_INSET_MAC_PPPOE, ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_qinq_pppoes_proto, ICE_SW_INSET_MAC_PPPOE_PROTO, ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_qinq_pppoes_ipv4, ICE_SW_INSET_MAC_PPPOE_IPV4, ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_ipv4_pfcp, ICE_INSET_NONE, ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_ipv6_pfcp, ICE_INSET_NONE, ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_qinq_ipv4, ICE_SW_INSET_MAC_QINQ_IPV4, ICE_INSET_NONE, ICE_INSET_NONE},
+ {pattern_eth_qinq_ipv4_tcp, ICE_SW_INSET_MAC_QINQ_IPV4_TCP, ICE_INSET_NONE, ICE_INSET_NONE},
+ {pattern_eth_qinq_ipv4_udp, ICE_SW_INSET_MAC_QINQ_IPV4_UDP, ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_qinq_ipv6, ICE_SW_INSET_MAC_QINQ_IPV6, ICE_INSET_NONE, ICE_INSET_NONE},
+ {pattern_eth_qinq_ipv6_tcp, ICE_SW_INSET_MAC_QINQ_IPV6_TCP, ICE_INSET_NONE, ICE_INSET_NONE},
+ {pattern_eth_qinq_ipv6_udp, ICE_SW_INSET_MAC_QINQ_IPV6_UDP, ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_qinq_pppoes, ICE_SW_INSET_MAC_PPPOE, ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_qinq_pppoes_proto, ICE_SW_INSET_MAC_PPPOE_PROTO, ICE_INSET_NONE, ICE_INSET_NONE},
{pattern_eth_qinq_pppoes_ipv4, ICE_SW_INSET_MAC_PPPOE_IPV4, ICE_INSET_NONE, ICE_INSET_NONE},
return false;
}
if (gtp_psc_spec && gtp_psc_mask) {
- if (gtp_psc_mask->pdu_type) {
+ if (gtp_psc_mask->hdr.type) {
rte_flow_error_set(error, EINVAL,
RTE_FLOW_ERROR_TYPE_ITEM,
item,
return false;
}
input = &outer_input_set;
- if (gtp_psc_mask->qfi)
+ if (gtp_psc_mask->hdr.qfi)
*input |= ICE_INSET_GTPU_QFI;
list[t].type = ICE_GTP;
list[t].h_u.gtp_hdr.qfi =
- gtp_psc_spec->qfi;
+ gtp_psc_spec->hdr.qfi;
list[t].m_u.gtp_hdr.qfi =
- gtp_psc_mask->qfi;
+ gtp_psc_mask->hdr.qfi;
input_set_byte += 1;
t++;
}
rule_info->sw_act.src = rule_info->sw_act.vsi_handle;
rule_info->sw_act.flag = ICE_FLTR_RX;
rule_info->rx = 1;
- rule_info->priority = priority + 5;
+ /* 0 denotes lowest priority of recipe and highest priority
+ * of rte_flow. Change rte_flow priority into recipe priority.
+ */
+ rule_info->priority = ICE_SW_PRI_BASE - priority;
return 0;
}
rule_info->sw_act.vsi_handle = vsi->idx;
rule_info->rx = 1;
rule_info->sw_act.src = vsi->idx;
- rule_info->priority = priority + 5;
+ /* 0 denotes lowest priority of recipe and highest priority
+ * of rte_flow. Change rte_flow priority into recipe priority.
+ */
+ rule_info->priority = ICE_SW_PRI_BASE - priority;
return 0;