#include <rte_string_fns.h>
#include <rte_pci.h>
#include <rte_bus_pci.h>
-#include <rte_ethdev_driver.h>
-#include <rte_ethdev_pci.h>
+#include <ethdev_driver.h>
+#include <ethdev_pci.h>
#include <rte_malloc.h>
#include <rte_alarm.h>
#include "igc_logs.h"
#include "igc_txrx.h"
+#include "igc_filter.h"
+#include "igc_flow.h"
#define IGC_INTEL_VENDOR_ID 0x8086
/* External VLAN Enable bit mask */
#define IGC_CTRL_EXT_EXT_VLAN (1u << 26)
+/* Speed select */
+#define IGC_CTRL_SPEED_MASK (7u << 8)
+#define IGC_CTRL_SPEED_2500 (6u << 8)
+
+/* External VLAN Ether Type bit mask and shift */
+#define IGC_VET_EXT 0xFFFF0000
+#define IGC_VET_EXT_SHIFT 16
+
+/* Force EEE Auto-negotiation */
+#define IGC_EEER_EEE_FRC_AN (1u << 28)
+
/* Per Queue Good Packets Received Count */
#define IGC_PQGPRC(idx) (0x10010 + 0x100 * (idx))
/* Per Queue Good Octets Received Count */
static int eth_igc_configure(struct rte_eth_dev *dev);
static int eth_igc_link_update(struct rte_eth_dev *dev, int wait_to_complete);
-static void eth_igc_stop(struct rte_eth_dev *dev);
+static int eth_igc_stop(struct rte_eth_dev *dev);
static int eth_igc_start(struct rte_eth_dev *dev);
static int eth_igc_set_link_up(struct rte_eth_dev *dev);
static int eth_igc_set_link_down(struct rte_eth_dev *dev);
-static void eth_igc_close(struct rte_eth_dev *dev);
+static int eth_igc_close(struct rte_eth_dev *dev);
static int eth_igc_reset(struct rte_eth_dev *dev);
static int eth_igc_promiscuous_enable(struct rte_eth_dev *dev);
static int eth_igc_promiscuous_disable(struct rte_eth_dev *dev);
eth_igc_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf);
static int
eth_igc_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf);
+static int eth_igc_rss_reta_update(struct rte_eth_dev *dev,
+ struct rte_eth_rss_reta_entry64 *reta_conf,
+ uint16_t reta_size);
+static int eth_igc_rss_reta_query(struct rte_eth_dev *dev,
+ struct rte_eth_rss_reta_entry64 *reta_conf,
+ uint16_t reta_size);
+static int eth_igc_rss_hash_update(struct rte_eth_dev *dev,
+ struct rte_eth_rss_conf *rss_conf);
+static int eth_igc_rss_hash_conf_get(struct rte_eth_dev *dev,
+ struct rte_eth_rss_conf *rss_conf);
+static int
+eth_igc_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
+static int eth_igc_vlan_offload_set(struct rte_eth_dev *dev, int mask);
+static int eth_igc_vlan_tpid_set(struct rte_eth_dev *dev,
+ enum rte_vlan_type vlan_type, uint16_t tpid);
static const struct eth_dev_ops eth_igc_ops = {
.dev_configure = eth_igc_configure,
.rx_queue_setup = eth_igc_rx_queue_setup,
.rx_queue_release = eth_igc_rx_queue_release,
- .rx_queue_count = eth_igc_rx_queue_count,
- .rx_descriptor_done = eth_igc_rx_descriptor_done,
- .rx_descriptor_status = eth_igc_rx_descriptor_status,
- .tx_descriptor_status = eth_igc_tx_descriptor_status,
.tx_queue_setup = eth_igc_tx_queue_setup,
.tx_queue_release = eth_igc_tx_queue_release,
.tx_done_cleanup = eth_igc_tx_done_cleanup,
.rx_queue_intr_disable = eth_igc_rx_queue_intr_disable,
.flow_ctrl_get = eth_igc_flow_ctrl_get,
.flow_ctrl_set = eth_igc_flow_ctrl_set,
+ .reta_update = eth_igc_rss_reta_update,
+ .reta_query = eth_igc_rss_reta_query,
+ .rss_hash_update = eth_igc_rss_hash_update,
+ .rss_hash_conf_get = eth_igc_rss_hash_conf_get,
+ .vlan_filter_set = eth_igc_vlan_filter_set,
+ .vlan_offload_set = eth_igc_vlan_offload_set,
+ .vlan_tpid_set = eth_igc_vlan_tpid_set,
+ .vlan_strip_queue_set = eth_igc_vlan_strip_queue_set,
+ .flow_ops_get = eth_igc_flow_ops_get,
};
/*
PMD_INIT_FUNC_TRACE();
+ if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
+ dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
+
ret = igc_check_mq_mode(dev);
if (ret != 0)
return ret;
pci_dev->addr.bus,
pci_dev->addr.devid,
pci_dev->addr.function);
- _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
- NULL);
+ rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
}
}
* This routine disables all traffic on the adapter by issuing a
* global reset on the MAC.
*/
-static void
+static int
eth_igc_stop(struct rte_eth_dev *dev)
{
struct igc_adapter *adapter = IGC_DEV_PRIVATE(dev);
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
struct rte_eth_link link;
+ dev->data->dev_started = 0;
adapter->stopped = 1;
/* disable receive and transmit */
/* disable all wake up */
IGC_WRITE_REG(hw, IGC_WUC, 0);
+ /* disable checking EEE operation in MAC loopback mode */
+ igc_read_reg_check_clear_bits(hw, IGC_EEER, IGC_EEER_EEE_FRC_AN);
+
/* Set bit for Go Link disconnect */
igc_read_reg_check_set_bits(hw, IGC_82580_PHY_POWER_MGMT,
IGC_82580_PM_GO_LINKD);
rte_free(intr_handle->intr_vec);
intr_handle->intr_vec = NULL;
}
+
+ return 0;
}
/*
igc_clear_hw_cntrs_base_generic(hw);
+ /* VLAN Offload Settings */
+ eth_igc_vlan_offload_set(dev,
+ ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
+ ETH_VLAN_EXTEND_MASK);
+
/* Setup link speed and duplex */
speeds = &dev->data->dev_conf.link_speeds;
if (*speeds == ETH_LINK_SPEED_AUTONEG) {
hw->mac.autoneg = 1;
} else {
int num_speeds = 0;
- bool autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
- /* Reset */
+ if (*speeds & ETH_LINK_SPEED_FIXED) {
+ PMD_DRV_LOG(ERR,
+ "Force speed mode currently not supported");
+ igc_dev_clear_queues(dev);
+ return -EINVAL;
+ }
+
hw->phy.autoneg_advertised = 0;
+ hw->mac.autoneg = 1;
if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
- ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G |
- ETH_LINK_SPEED_FIXED)) {
+ ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G)) {
num_speeds = -1;
goto error_invalid_config;
}
hw->phy.autoneg_advertised |= ADVERTISE_2500_FULL;
num_speeds++;
}
- if (num_speeds == 0 || (!autoneg && num_speeds > 1))
+ if (num_speeds == 0)
goto error_invalid_config;
-
- /* Set/reset the mac.autoneg based on the link speed,
- * fixed or not
- */
- if (!autoneg) {
- hw->mac.autoneg = 0;
- hw->mac.forced_speed_duplex =
- hw->phy.autoneg_advertised;
- } else {
- hw->mac.autoneg = 1;
- }
}
igc_setup_link(hw);
eth_igc_rxtx_control(dev, true);
eth_igc_link_update(dev, 0);
+ /* configure MAC-loopback mode */
+ if (dev->data->dev_conf.lpbk_mode == 1) {
+ uint32_t reg_val;
+
+ reg_val = IGC_READ_REG(hw, IGC_CTRL);
+ reg_val &= ~IGC_CTRL_SPEED_MASK;
+ reg_val |= IGC_CTRL_SLU | IGC_CTRL_FRCSPD |
+ IGC_CTRL_FRCDPX | IGC_CTRL_FD | IGC_CTRL_SPEED_2500;
+ IGC_WRITE_REG(hw, IGC_CTRL, reg_val);
+
+ igc_read_reg_check_set_bits(hw, IGC_EEER, IGC_EEER_EEE_FRC_AN);
+ }
+
return 0;
error_invalid_config:
dev->data->nb_tx_queues = 0;
}
-static void
+static int
eth_igc_close(struct rte_eth_dev *dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
struct igc_adapter *adapter = IGC_DEV_PRIVATE(dev);
int retry = 0;
+ int ret = 0;
PMD_INIT_FUNC_TRACE();
+ if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+ return 0;
if (!adapter->stopped)
- eth_igc_stop(dev);
+ ret = eth_igc_stop(dev);
+
+ igc_flow_flush(dev, NULL);
+ igc_clear_all_filter(dev);
igc_intr_other_disable(dev);
do {
/* Reset any pending lock */
igc_reset_swfw_lock(hw);
+
+ return ret;
}
static void
PMD_INIT_FUNC_TRACE();
dev->dev_ops = ð_igc_ops;
+ dev->rx_descriptor_done = eth_igc_rx_descriptor_done;
+ dev->rx_queue_count = eth_igc_rx_queue_count;
+ dev->rx_descriptor_status = eth_igc_rx_descriptor_status;
+ dev->tx_descriptor_status = eth_igc_tx_descriptor_status;
/*
* for secondary processes, we don't initialize any further as primary
return 0;
rte_eth_copy_pci_info(dev, pci_dev);
+ dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
hw->back = pci_dev;
hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
goto err_late;
}
- /* Pass the information to the rte_eth_dev_close() that it should also
- * release the private port resources.
- */
- dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
-
hw->mac.get_link_status = 1;
igc->stopped = 0;
igc->rxq_stats_map[i] = -1;
}
+ igc_flow_init(dev);
+ igc_clear_all_filter(dev);
return 0;
err_late:
eth_igc_dev_uninit(__rte_unused struct rte_eth_dev *eth_dev)
{
PMD_INIT_FUNC_TRACE();
-
- if (rte_eal_process_type() != RTE_PROC_PRIMARY)
- return 0;
-
eth_igc_close(eth_dev);
return 0;
}
fw.eep_build);
}
}
+ if (ret < 0)
+ return -EINVAL;
ret += 1; /* add the size of '\0' */
- if (fw_size < (u32)ret)
+ if (fw_size < (size_t)ret)
return ret;
else
return 0;
dev_info->max_mac_addrs = hw->mac.rar_entry_count;
dev_info->rx_offload_capa = IGC_RX_OFFLOAD_ALL;
dev_info->tx_offload_capa = IGC_TX_OFFLOAD_ALL;
+ dev_info->rx_queue_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
dev_info->max_rx_queues = IGC_QUEUE_PAIRS_NUM;
dev_info->max_tx_queues = IGC_QUEUE_PAIRS_NUM;
return -EINVAL;
/*
- * refuse mtu that requires the support of scattered packets when
- * this feature has not been enabled before.
+ * If device is started, refuse mtu that requires the support of
+ * scattered packets when this feature has not been enabled before.
*/
- if (!dev->data->scattered_rx &&
- frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
+ if (dev->data->dev_started && !dev->data->scattered_rx &&
+ frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
+ PMD_INIT_LOG(ERR, "Stop port first.");
return -EINVAL;
+ }
rctl = IGC_READ_REG(hw, IGC_RCTL);
/* Rx Errors */
rte_stats->imissed = stats->mpc;
- rte_stats->ierrors = stats->crcerrs +
- stats->rlec + stats->ruc + stats->roc +
+ rte_stats->ierrors = stats->crcerrs + stats->rlec +
stats->rxerrc + stats->algnerrc;
/* Tx Errors */
return -EIO;
}
+static int
+eth_igc_rss_reta_update(struct rte_eth_dev *dev,
+ struct rte_eth_rss_reta_entry64 *reta_conf,
+ uint16_t reta_size)
+{
+ struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
+ uint16_t i;
+
+ if (reta_size != ETH_RSS_RETA_SIZE_128) {
+ PMD_DRV_LOG(ERR,
+ "The size of RSS redirection table configured(%d) doesn't match the number hardware can supported(%d)",
+ reta_size, ETH_RSS_RETA_SIZE_128);
+ return -EINVAL;
+ }
+
+ RTE_BUILD_BUG_ON(ETH_RSS_RETA_SIZE_128 % IGC_RSS_RDT_REG_SIZE);
+
+ /* set redirection table */
+ for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IGC_RSS_RDT_REG_SIZE) {
+ union igc_rss_reta_reg reta, reg;
+ uint16_t idx, shift;
+ uint8_t j, mask;
+
+ idx = i / RTE_RETA_GROUP_SIZE;
+ shift = i % RTE_RETA_GROUP_SIZE;
+ mask = (uint8_t)((reta_conf[idx].mask >> shift) &
+ IGC_RSS_RDT_REG_SIZE_MASK);
+
+ /* if no need to update the register */
+ if (!mask ||
+ shift > (RTE_RETA_GROUP_SIZE - IGC_RSS_RDT_REG_SIZE))
+ continue;
+
+ /* check mask whether need to read the register value first */
+ if (mask == IGC_RSS_RDT_REG_SIZE_MASK)
+ reg.dword = 0;
+ else
+ reg.dword = IGC_READ_REG_LE_VALUE(hw,
+ IGC_RETA(i / IGC_RSS_RDT_REG_SIZE));
+
+ /* update the register */
+ RTE_BUILD_BUG_ON(sizeof(reta.bytes) != IGC_RSS_RDT_REG_SIZE);
+ for (j = 0; j < IGC_RSS_RDT_REG_SIZE; j++) {
+ if (mask & (1u << j))
+ reta.bytes[j] =
+ (uint8_t)reta_conf[idx].reta[shift + j];
+ else
+ reta.bytes[j] = reg.bytes[j];
+ }
+ IGC_WRITE_REG_LE_VALUE(hw,
+ IGC_RETA(i / IGC_RSS_RDT_REG_SIZE), reta.dword);
+ }
+
+ return 0;
+}
+
+static int
+eth_igc_rss_reta_query(struct rte_eth_dev *dev,
+ struct rte_eth_rss_reta_entry64 *reta_conf,
+ uint16_t reta_size)
+{
+ struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
+ uint16_t i;
+
+ if (reta_size != ETH_RSS_RETA_SIZE_128) {
+ PMD_DRV_LOG(ERR,
+ "The size of RSS redirection table configured(%d) doesn't match the number hardware can supported(%d)",
+ reta_size, ETH_RSS_RETA_SIZE_128);
+ return -EINVAL;
+ }
+
+ RTE_BUILD_BUG_ON(ETH_RSS_RETA_SIZE_128 % IGC_RSS_RDT_REG_SIZE);
+
+ /* read redirection table */
+ for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IGC_RSS_RDT_REG_SIZE) {
+ union igc_rss_reta_reg reta;
+ uint16_t idx, shift;
+ uint8_t j, mask;
+
+ idx = i / RTE_RETA_GROUP_SIZE;
+ shift = i % RTE_RETA_GROUP_SIZE;
+ mask = (uint8_t)((reta_conf[idx].mask >> shift) &
+ IGC_RSS_RDT_REG_SIZE_MASK);
+
+ /* if no need to read register */
+ if (!mask ||
+ shift > (RTE_RETA_GROUP_SIZE - IGC_RSS_RDT_REG_SIZE))
+ continue;
+
+ /* read register and get the queue index */
+ RTE_BUILD_BUG_ON(sizeof(reta.bytes) != IGC_RSS_RDT_REG_SIZE);
+ reta.dword = IGC_READ_REG_LE_VALUE(hw,
+ IGC_RETA(i / IGC_RSS_RDT_REG_SIZE));
+ for (j = 0; j < IGC_RSS_RDT_REG_SIZE; j++) {
+ if (mask & (1u << j))
+ reta_conf[idx].reta[shift + j] = reta.bytes[j];
+ }
+ }
+
+ return 0;
+}
+
+static int
+eth_igc_rss_hash_update(struct rte_eth_dev *dev,
+ struct rte_eth_rss_conf *rss_conf)
+{
+ struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
+ igc_hw_rss_hash_set(hw, rss_conf);
+ return 0;
+}
+
+static int
+eth_igc_rss_hash_conf_get(struct rte_eth_dev *dev,
+ struct rte_eth_rss_conf *rss_conf)
+{
+ struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
+ uint32_t *hash_key = (uint32_t *)rss_conf->rss_key;
+ uint32_t mrqc;
+ uint64_t rss_hf;
+
+ if (hash_key != NULL) {
+ int i;
+
+ /* if not enough space for store hash key */
+ if (rss_conf->rss_key_len != IGC_HKEY_SIZE) {
+ PMD_DRV_LOG(ERR,
+ "RSS hash key size %u in parameter doesn't match the hardware hash key size %u",
+ rss_conf->rss_key_len, IGC_HKEY_SIZE);
+ return -EINVAL;
+ }
+
+ /* read RSS key from register */
+ for (i = 0; i < IGC_HKEY_MAX_INDEX; i++)
+ hash_key[i] = IGC_READ_REG_LE_VALUE(hw, IGC_RSSRK(i));
+ }
+
+ /* get RSS functions configured in MRQC register */
+ mrqc = IGC_READ_REG(hw, IGC_MRQC);
+ if ((mrqc & IGC_MRQC_ENABLE_RSS_4Q) == 0)
+ return 0;
+
+ rss_hf = 0;
+ if (mrqc & IGC_MRQC_RSS_FIELD_IPV4)
+ rss_hf |= ETH_RSS_IPV4;
+ if (mrqc & IGC_MRQC_RSS_FIELD_IPV4_TCP)
+ rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
+ if (mrqc & IGC_MRQC_RSS_FIELD_IPV6)
+ rss_hf |= ETH_RSS_IPV6;
+ if (mrqc & IGC_MRQC_RSS_FIELD_IPV6_EX)
+ rss_hf |= ETH_RSS_IPV6_EX;
+ if (mrqc & IGC_MRQC_RSS_FIELD_IPV6_TCP)
+ rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
+ if (mrqc & IGC_MRQC_RSS_FIELD_IPV6_TCP_EX)
+ rss_hf |= ETH_RSS_IPV6_TCP_EX;
+ if (mrqc & IGC_MRQC_RSS_FIELD_IPV4_UDP)
+ rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
+ if (mrqc & IGC_MRQC_RSS_FIELD_IPV6_UDP)
+ rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
+ if (mrqc & IGC_MRQC_RSS_FIELD_IPV6_UDP_EX)
+ rss_hf |= ETH_RSS_IPV6_UDP_EX;
+
+ rss_conf->rss_hf |= rss_hf;
+ return 0;
+}
+
+static int
+eth_igc_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
+{
+ struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
+ struct igc_vfta *shadow_vfta = IGC_DEV_PRIVATE_VFTA(dev);
+ uint32_t vfta;
+ uint32_t vid_idx;
+ uint32_t vid_bit;
+
+ vid_idx = (vlan_id >> IGC_VFTA_ENTRY_SHIFT) & IGC_VFTA_ENTRY_MASK;
+ vid_bit = 1u << (vlan_id & IGC_VFTA_ENTRY_BIT_SHIFT_MASK);
+ vfta = shadow_vfta->vfta[vid_idx];
+ if (on)
+ vfta |= vid_bit;
+ else
+ vfta &= ~vid_bit;
+ IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, vid_idx, vfta);
+
+ /* update local VFTA copy */
+ shadow_vfta->vfta[vid_idx] = vfta;
+
+ return 0;
+}
+
+static void
+igc_vlan_hw_filter_disable(struct rte_eth_dev *dev)
+{
+ struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
+ igc_read_reg_check_clear_bits(hw, IGC_RCTL,
+ IGC_RCTL_CFIEN | IGC_RCTL_VFE);
+}
+
+static void
+igc_vlan_hw_filter_enable(struct rte_eth_dev *dev)
+{
+ struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
+ struct igc_vfta *shadow_vfta = IGC_DEV_PRIVATE_VFTA(dev);
+ uint32_t reg_val;
+ int i;
+
+ /* Filter Table Enable, CFI not used for packet acceptance */
+ reg_val = IGC_READ_REG(hw, IGC_RCTL);
+ reg_val &= ~IGC_RCTL_CFIEN;
+ reg_val |= IGC_RCTL_VFE;
+ IGC_WRITE_REG(hw, IGC_RCTL, reg_val);
+
+ /* restore VFTA table */
+ for (i = 0; i < IGC_VFTA_SIZE; i++)
+ IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, i, shadow_vfta->vfta[i]);
+}
+
+static void
+igc_vlan_hw_strip_disable(struct rte_eth_dev *dev)
+{
+ struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
+
+ igc_read_reg_check_clear_bits(hw, IGC_CTRL, IGC_CTRL_VME);
+}
+
+static void
+igc_vlan_hw_strip_enable(struct rte_eth_dev *dev)
+{
+ struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
+
+ igc_read_reg_check_set_bits(hw, IGC_CTRL, IGC_CTRL_VME);
+}
+
+static int
+igc_vlan_hw_extend_disable(struct rte_eth_dev *dev)
+{
+ struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
+ uint32_t ctrl_ext;
+
+ ctrl_ext = IGC_READ_REG(hw, IGC_CTRL_EXT);
+
+ /* if extend vlan hasn't been enabled */
+ if ((ctrl_ext & IGC_CTRL_EXT_EXT_VLAN) == 0)
+ return 0;
+
+ if ((dev->data->dev_conf.rxmode.offloads &
+ DEV_RX_OFFLOAD_JUMBO_FRAME) == 0)
+ goto write_ext_vlan;
+
+ /* Update maximum packet length */
+ if (dev->data->dev_conf.rxmode.max_rx_pkt_len <
+ RTE_ETHER_MIN_MTU + VLAN_TAG_SIZE) {
+ PMD_DRV_LOG(ERR, "Maximum packet length %u error, min is %u",
+ dev->data->dev_conf.rxmode.max_rx_pkt_len,
+ VLAN_TAG_SIZE + RTE_ETHER_MIN_MTU);
+ return -EINVAL;
+ }
+ dev->data->dev_conf.rxmode.max_rx_pkt_len -= VLAN_TAG_SIZE;
+ IGC_WRITE_REG(hw, IGC_RLPML,
+ dev->data->dev_conf.rxmode.max_rx_pkt_len);
+
+write_ext_vlan:
+ IGC_WRITE_REG(hw, IGC_CTRL_EXT, ctrl_ext & ~IGC_CTRL_EXT_EXT_VLAN);
+ return 0;
+}
+
+static int
+igc_vlan_hw_extend_enable(struct rte_eth_dev *dev)
+{
+ struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
+ uint32_t ctrl_ext;
+
+ ctrl_ext = IGC_READ_REG(hw, IGC_CTRL_EXT);
+
+ /* if extend vlan has been enabled */
+ if (ctrl_ext & IGC_CTRL_EXT_EXT_VLAN)
+ return 0;
+
+ if ((dev->data->dev_conf.rxmode.offloads &
+ DEV_RX_OFFLOAD_JUMBO_FRAME) == 0)
+ goto write_ext_vlan;
+
+ /* Update maximum packet length */
+ if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
+ MAX_RX_JUMBO_FRAME_SIZE - VLAN_TAG_SIZE) {
+ PMD_DRV_LOG(ERR, "Maximum packet length %u error, max is %u",
+ dev->data->dev_conf.rxmode.max_rx_pkt_len +
+ VLAN_TAG_SIZE, MAX_RX_JUMBO_FRAME_SIZE);
+ return -EINVAL;
+ }
+ dev->data->dev_conf.rxmode.max_rx_pkt_len += VLAN_TAG_SIZE;
+ IGC_WRITE_REG(hw, IGC_RLPML,
+ dev->data->dev_conf.rxmode.max_rx_pkt_len);
+
+write_ext_vlan:
+ IGC_WRITE_REG(hw, IGC_CTRL_EXT, ctrl_ext | IGC_CTRL_EXT_EXT_VLAN);
+ return 0;
+}
+
+static int
+eth_igc_vlan_offload_set(struct rte_eth_dev *dev, int mask)
+{
+ struct rte_eth_rxmode *rxmode;
+
+ rxmode = &dev->data->dev_conf.rxmode;
+ if (mask & ETH_VLAN_STRIP_MASK) {
+ if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
+ igc_vlan_hw_strip_enable(dev);
+ else
+ igc_vlan_hw_strip_disable(dev);
+ }
+
+ if (mask & ETH_VLAN_FILTER_MASK) {
+ if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
+ igc_vlan_hw_filter_enable(dev);
+ else
+ igc_vlan_hw_filter_disable(dev);
+ }
+
+ if (mask & ETH_VLAN_EXTEND_MASK) {
+ if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
+ return igc_vlan_hw_extend_enable(dev);
+ else
+ return igc_vlan_hw_extend_disable(dev);
+ }
+
+ return 0;
+}
+
+static int
+eth_igc_vlan_tpid_set(struct rte_eth_dev *dev,
+ enum rte_vlan_type vlan_type,
+ uint16_t tpid)
+{
+ struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
+ uint32_t reg_val;
+
+ /* only outer TPID of double VLAN can be configured*/
+ if (vlan_type == ETH_VLAN_TYPE_OUTER) {
+ reg_val = IGC_READ_REG(hw, IGC_VET);
+ reg_val = (reg_val & (~IGC_VET_EXT)) |
+ ((uint32_t)tpid << IGC_VET_EXT_SHIFT);
+ IGC_WRITE_REG(hw, IGC_VET, reg_val);
+
+ return 0;
+ }
+
+ /* all other TPID values are read-only*/
+ PMD_DRV_LOG(ERR, "Not supported");
+ return -ENOTSUP;
+}
+
static int
eth_igc_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
struct rte_pci_device *pci_dev)