ionic_lif_reset(struct ionic_lif *lif)
{
struct ionic_dev *idev = &lif->adapter->idev;
+ int err;
IONIC_PRINT_CALL();
ionic_dev_cmd_lif_reset(idev, lif->index);
- ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
+ err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
+ if (err)
+ IONIC_PRINT(WARNING, "Failed to reset %s", lif->name);
+}
+
+static void
+ionic_lif_get_abs_stats(const struct ionic_lif *lif, struct rte_eth_stats *stats)
+{
+ struct ionic_lif_stats *ls = &lif->info->stats;
+ uint32_t i;
+ uint32_t num_rx_q_counters = RTE_MIN(lif->nrxqcqs, (uint32_t)
+ RTE_ETHDEV_QUEUE_STAT_CNTRS);
+ uint32_t num_tx_q_counters = RTE_MIN(lif->ntxqcqs, (uint32_t)
+ RTE_ETHDEV_QUEUE_STAT_CNTRS);
+
+ memset(stats, 0, sizeof(*stats));
+
+ if (ls == NULL) {
+ IONIC_PRINT(DEBUG, "Stats on port %u not yet initialized",
+ lif->port_id);
+ return;
+ }
+
+ /* RX */
+
+ stats->ipackets = ls->rx_ucast_packets +
+ ls->rx_mcast_packets +
+ ls->rx_bcast_packets;
+
+ stats->ibytes = ls->rx_ucast_bytes +
+ ls->rx_mcast_bytes +
+ ls->rx_bcast_bytes;
+
+ for (i = 0; i < lif->nrxqcqs; i++) {
+ struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats.rx;
+ stats->imissed +=
+ rx_stats->no_cb_arg +
+ rx_stats->bad_cq_status +
+ rx_stats->no_room +
+ rx_stats->bad_len;
+ }
+
+ stats->imissed +=
+ ls->rx_ucast_drop_packets +
+ ls->rx_mcast_drop_packets +
+ ls->rx_bcast_drop_packets;
+
+ stats->imissed +=
+ ls->rx_queue_empty +
+ ls->rx_dma_error +
+ ls->rx_queue_disabled +
+ ls->rx_desc_fetch_error +
+ ls->rx_desc_data_error;
+
+ for (i = 0; i < num_rx_q_counters; i++) {
+ struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats.rx;
+ stats->q_ipackets[i] = rx_stats->packets;
+ stats->q_ibytes[i] = rx_stats->bytes;
+ stats->q_errors[i] =
+ rx_stats->no_cb_arg +
+ rx_stats->bad_cq_status +
+ rx_stats->no_room +
+ rx_stats->bad_len;
+ }
+
+ /* TX */
+
+ stats->opackets = ls->tx_ucast_packets +
+ ls->tx_mcast_packets +
+ ls->tx_bcast_packets;
+
+ stats->obytes = ls->tx_ucast_bytes +
+ ls->tx_mcast_bytes +
+ ls->tx_bcast_bytes;
+
+ for (i = 0; i < lif->ntxqcqs; i++) {
+ struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats.tx;
+ stats->oerrors += tx_stats->drop;
+ }
+
+ stats->oerrors +=
+ ls->tx_ucast_drop_packets +
+ ls->tx_mcast_drop_packets +
+ ls->tx_bcast_drop_packets;
+
+ stats->oerrors +=
+ ls->tx_dma_error +
+ ls->tx_queue_disabled +
+ ls->tx_desc_fetch_error +
+ ls->tx_desc_data_error;
+
+ for (i = 0; i < num_tx_q_counters; i++) {
+ struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats.tx;
+ stats->q_opackets[i] = tx_stats->packets;
+ stats->q_obytes[i] = tx_stats->bytes;
+ }
+}
+
+void
+ionic_lif_get_stats(const struct ionic_lif *lif,
+ struct rte_eth_stats *stats)
+{
+ ionic_lif_get_abs_stats(lif, stats);
+
+ stats->ipackets -= lif->stats_base.ipackets;
+ stats->opackets -= lif->stats_base.opackets;
+ stats->ibytes -= lif->stats_base.ibytes;
+ stats->obytes -= lif->stats_base.obytes;
+ stats->imissed -= lif->stats_base.imissed;
+ stats->ierrors -= lif->stats_base.ierrors;
+ stats->oerrors -= lif->stats_base.oerrors;
+ stats->rx_nombuf -= lif->stats_base.rx_nombuf;
+}
+
+void
+ionic_lif_reset_stats(struct ionic_lif *lif)
+{
+ uint32_t i;
+
+ for (i = 0; i < lif->nrxqcqs; i++) {
+ memset(&lif->rxqcqs[i]->stats.rx, 0,
+ sizeof(struct ionic_rx_stats));
+ memset(&lif->txqcqs[i]->stats.tx, 0,
+ sizeof(struct ionic_tx_stats));
+ }
+
+ ionic_lif_get_abs_stats(lif, &lif->stats_base);
+}
+
+void
+ionic_lif_get_hw_stats(struct ionic_lif *lif, struct ionic_lif_stats *stats)
+{
+ uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t);
+ uint64_t *stats64 = (uint64_t *)stats;
+ uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats;
+ uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base;
+
+ for (i = 0; i < count; i++)
+ stats64[i] = lif_stats64[i] - lif_stats64_base[i];
+}
+
+void
+ionic_lif_reset_hw_stats(struct ionic_lif *lif)
+{
+ uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t);
+ uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats;
+ uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base;
+
+ for (i = 0; i < count; i++)
+ lif_stats64_base[i] = lif_stats64[i];
}
static int
}
void
-ionic_dev_remove_mac(struct rte_eth_dev *eth_dev, uint32_t index __rte_unused)
+ionic_dev_remove_mac(struct rte_eth_dev *eth_dev, uint32_t index)
{
struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
struct ionic_adapter *adapter = lif->adapter;
+ struct rte_ether_addr *mac_addr;
IONIC_PRINT_CALL();
return;
}
- if (!rte_is_valid_assigned_ether_addr(ð_dev->data->mac_addrs[index]))
+ mac_addr = ð_dev->data->mac_addrs[index];
+
+ if (!rte_is_valid_assigned_ether_addr(mac_addr))
return;
- ionic_lif_addr_del(lif, (const uint8_t *)
- ð_dev->data->mac_addrs[index]);
+ ionic_lif_addr_del(lif, (const uint8_t *)mac_addr);
}
int
if (err)
return err;
- lif->mtu = new_mtu;
-
return 0;
}
/*
* Note: interrupt handler is called for index = 0 only
* (we use interrupts for the notifyq only anyway,
- * which hash index = 0)
+ * which has index = 0)
*/
for (index = 0; index < adapter->nintrs; index++)
uint32_t desc_size,
uint32_t cq_desc_size,
uint32_t sg_desc_size,
- uint32_t pid, struct ionic_qcq **qcq)
+ struct ionic_qcq **qcq)
{
struct ionic_dev *idev = &lif->adapter->idev;
struct ionic_qcq *new;
new->q.type = type;
err = ionic_q_init(lif, idev, &new->q, index, num_descs,
- desc_size, sg_desc_size, pid);
+ desc_size, sg_desc_size);
if (err) {
IONIC_PRINT(ERR, "Queue initialization failed");
return err;
ionic_q_sg_map(&new->q, sg_base, sg_base_pa);
}
- IONIC_PRINT(DEBUG, "Q-Base-PA = %ju CQ-Base-PA = %ju "
- "SG-base-PA = %ju",
+ IONIC_PRINT(DEBUG, "Q-Base-PA = %#jx CQ-Base-PA = %#jx "
+ "SG-base-PA = %#jx",
q_base_pa, cq_base_pa, sg_base_pa);
ionic_q_map(&new->q, q_base, q_base_pa);
sizeof(struct ionic_rxq_desc),
sizeof(struct ionic_rxq_comp),
sizeof(struct ionic_rxq_sg_desc),
- lif->kern_pid, &lif->rxqcqs[index]);
+ &lif->rxqcqs[index]);
if (err)
return err;
sizeof(struct ionic_txq_desc),
sizeof(struct ionic_txq_comp),
sizeof(struct ionic_txq_sg_desc),
- lif->kern_pid, &lif->txqcqs[index]);
+ &lif->txqcqs[index]);
if (err)
return err;
sizeof(struct ionic_admin_cmd),
sizeof(struct ionic_admin_comp),
0,
- lif->kern_pid, &lif->adminqcq);
+ &lif->adminqcq);
if (err)
return err;
sizeof(struct ionic_notifyq_cmd),
sizeof(union ionic_notifyq_comp),
0,
- lif->kern_pid, &lif->notifyqcq);
+ &lif->notifyqcq);
if (err)
return err;
int dbpage_num;
int err;
- snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index);
+ /*
+ * lif->name was zeroed on allocation.
+ * Copy (sizeof() - 1) bytes to ensure that it is NULL terminated.
+ */
+ memcpy(lif->name, lif->eth_dev->data->name, sizeof(lif->name) - 1);
+
+ IONIC_PRINT(DEBUG, "LIF: %s", lif->name);
IONIC_PRINT(DEBUG, "Allocating Lif Info");
rte_spinlock_init(&lif->adminq_lock);
rte_spinlock_init(&lif->adminq_service_lock);
- lif->kern_pid = 0;
-
dbpage_num = ionic_db_page_num(lif, 0);
lif->kern_dbpage = ionic_bus_map_dbpage(adapter, dbpage_num);
IONIC_PRINT(DEBUG, "Allocating Admin Queue");
- IONIC_PRINT(DEBUG, "Allocating Admin Queue");
-
err = ionic_admin_qcq_alloc(lif);
if (err) {
IONIC_PRINT(ERR, "Cannot allocate admin queue");
.index = q->index,
.flags = (IONIC_QINIT_F_IRQ | IONIC_QINIT_F_ENA),
.intr_index = qcq->intr.index,
- .pid = q->pid,
.ring_size = rte_log2_u32(q->num_descs),
.ring_base = q->base_pa,
}
};
- IONIC_PRINT(DEBUG, "notifyq_init.pid %d", ctx.cmd.q_init.pid);
IONIC_PRINT(DEBUG, "notifyq_init.index %d",
ctx.cmd.q_init.index);
IONIC_PRINT(DEBUG, "notifyq_init.ring_base 0x%" PRIx64 "",
ctx.cmd.q_init.ring_base);
IONIC_PRINT(DEBUG, "notifyq_init.ring_size %d",
ctx.cmd.q_init.ring_size);
+ IONIC_PRINT(DEBUG, "notifyq_init.ver %u", ctx.cmd.q_init.ver);
err = ionic_adminq_post_wait(lif, &ctx);
if (err)
.index = q->index,
.flags = IONIC_QINIT_F_SG,
.intr_index = cq->bound_intr->index,
- .pid = q->pid,
.ring_size = rte_log2_u32(q->num_descs),
.ring_base = q->base_pa,
.cq_ring_base = cq->base_pa,
};
int err;
- IONIC_PRINT(DEBUG, "txq_init.pid %d", ctx.cmd.q_init.pid);
IONIC_PRINT(DEBUG, "txq_init.index %d", ctx.cmd.q_init.index);
IONIC_PRINT(DEBUG, "txq_init.ring_base 0x%" PRIx64 "",
ctx.cmd.q_init.ring_base);
IONIC_PRINT(DEBUG, "txq_init.ring_size %d",
ctx.cmd.q_init.ring_size);
+ IONIC_PRINT(DEBUG, "txq_init.ver %u", ctx.cmd.q_init.ver);
err = ionic_adminq_post_wait(qcq->lif, &ctx);
if (err)
.index = q->index,
.flags = IONIC_QINIT_F_SG,
.intr_index = cq->bound_intr->index,
- .pid = q->pid,
.ring_size = rte_log2_u32(q->num_descs),
.ring_base = q->base_pa,
.cq_ring_base = cq->base_pa,
};
int err;
- IONIC_PRINT(DEBUG, "rxq_init.pid %d", ctx.cmd.q_init.pid);
IONIC_PRINT(DEBUG, "rxq_init.index %d", ctx.cmd.q_init.index);
IONIC_PRINT(DEBUG, "rxq_init.ring_base 0x%" PRIx64 "",
ctx.cmd.q_init.ring_base);
IONIC_PRINT(DEBUG, "rxq_init.ring_size %d",
ctx.cmd.q_init.ring_size);
+ IONIC_PRINT(DEBUG, "rxq_init.ver %u", ctx.cmd.q_init.ver);
err = ionic_adminq_post_wait(qcq->lif, &ctx);
if (err)
},
};
- snprintf(ctx.cmd.lif_setattr.name, sizeof(ctx.cmd.lif_setattr.name),
- "%d", lif->port_id);
+ memcpy(ctx.cmd.lif_setattr.name, lif->name,
+ sizeof(ctx.cmd.lif_setattr.name) - 1);
ionic_adminq_post_wait(lif, &ctx);
}
struct ionic_q_init_comp comp;
int err;
+ memset(&lif->stats_base, 0, sizeof(lif->stats_base));
+
ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa);
err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
ionic_dev_cmd_comp(idev, &comp);
| IONIC_ETH_HW_RX_HASH
| IONIC_ETH_HW_TX_SG
| IONIC_ETH_HW_RX_SG
+ | IONIC_ETH_HW_TX_CSUM
| IONIC_ETH_HW_RX_CSUM
| IONIC_ETH_HW_TSO
| IONIC_ETH_HW_TSO_IPV6
for (i = 0; i < lif->nrxqcqs; i++) {
struct ionic_qcq *rxq = lif->rxqcqs[i];
- if (!rxq->deferred_start) {
+ if (!(rxq->flags & IONIC_QCQ_F_DEFERRED)) {
err = ionic_dev_rx_queue_start(lif->eth_dev, i);
if (err)
for (i = 0; i < lif->ntxqcqs; i++) {
struct ionic_qcq *txq = lif->txqcqs[i];
- if (!txq->deferred_start) {
+ if (!(txq->flags & IONIC_QCQ_F_DEFERRED)) {
err = ionic_dev_tx_queue_start(lif->eth_dev, i);
if (err)
nintrs = nlifs * 1 /* notifyq */;
if (nintrs > dev_nintrs) {
- IONIC_PRINT(ERR, "At most %d intr queues supported, minimum required is %u",
+ IONIC_PRINT(ERR,
+ "At most %d intr supported, minimum req'd is %u",
dev_nintrs, nintrs);
return -ENOSPC;
}
git.droids-corp.org / dpdk.git / blobdiff