net/ngbe: support flow control

[dpdk.git] / drivers / net / ionic / ionic_lif.c

diff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c
index b8023e0..5e8fdf3 100644 (file)
--- a/drivers/net/ionic/ionic_lif.c
+++ b/drivers/net/ionic/ionic_lif.c
@@ -612,18 +612,18 @@ ionic_qcq_alloc(struct ionic_lif *lif,
        cq_size = num_descs * cq_desc_size;
        sg_size = num_descs * sg_desc_size;
 
-       total_size = RTE_ALIGN(q_size, PAGE_SIZE) +
-               RTE_ALIGN(cq_size, PAGE_SIZE);
+       total_size = RTE_ALIGN(q_size, rte_mem_page_size()) +
+                       RTE_ALIGN(cq_size, rte_mem_page_size());
        /*
         * Note: aligning q_size/cq_size is not enough due to cq_base address
         * aligning as q_base could be not aligned to the page.
-        * Adding PAGE_SIZE.
+        * Adding rte_mem_page_size().
         */
-       total_size += PAGE_SIZE;
+       total_size += rte_mem_page_size();
 
        if (flags & IONIC_QCQ_F_SG) {
-               total_size += RTE_ALIGN(sg_size, PAGE_SIZE);
-               total_size += PAGE_SIZE;
+               total_size += RTE_ALIGN(sg_size, rte_mem_page_size());
+               total_size += rte_mem_page_size();
        }
 
        new = rte_zmalloc("ionic", struct_size, 0);
@@ -636,7 +636,7 @@ ionic_qcq_alloc(struct ionic_lif *lif,
 
        new->q.info = rte_calloc_socket("ionic",
                                num_descs, sizeof(void *),
-                               PAGE_SIZE, socket_id);
+                               rte_mem_page_size(), socket_id);
        if (!new->q.info) {
                IONIC_PRINT(ERR, "Cannot allocate queue info");
                err = -ENOMEM;
@@ -673,13 +673,16 @@ ionic_qcq_alloc(struct ionic_lif *lif,
        q_base = new->base;
        q_base_pa = new->base_pa;
 
-       cq_base = (void *)RTE_ALIGN((uintptr_t)q_base + q_size, PAGE_SIZE);
-       cq_base_pa = RTE_ALIGN(q_base_pa + q_size, PAGE_SIZE);
+       cq_base = (void *)RTE_ALIGN((uintptr_t)q_base + q_size,
+                       rte_mem_page_size());
+       cq_base_pa = RTE_ALIGN(q_base_pa + q_size,
+                       rte_mem_page_size());
 
        if (flags & IONIC_QCQ_F_SG) {
                sg_base = (void *)RTE_ALIGN((uintptr_t)cq_base + cq_size,
-                       PAGE_SIZE);
-               sg_base_pa = RTE_ALIGN(cq_base_pa + cq_size, PAGE_SIZE);
+                               rte_mem_page_size());
+               sg_base_pa = RTE_ALIGN(cq_base_pa + cq_size,
+                               rte_mem_page_size());
                ionic_q_sg_map(&new->q, sg_base, sg_base_pa);
        }
 
@@ -1002,7 +1005,7 @@ ionic_lif_alloc(struct ionic_lif *lif)
 
        IONIC_PRINT(DEBUG, "Allocating Lif Info");
 
-       lif->info_sz = RTE_ALIGN(sizeof(*lif->info), PAGE_SIZE);
+       lif->info_sz = RTE_ALIGN(sizeof(*lif->info), rte_mem_page_size());
 
        lif->info_z = rte_eth_dma_zone_reserve(lif->eth_dev,
                "lif_info", 0 /* queue_idx*/,
@@ -1053,11 +1056,11 @@ ionic_lif_free_queues(struct ionic_lif *lif)
        uint32_t i;
 
        for (i = 0; i < lif->ntxqcqs; i++) {
-               ionic_dev_tx_queue_release(lif->eth_dev->data->tx_queues[i]);
+               ionic_dev_tx_queue_release(lif->eth_dev, i);
                lif->eth_dev->data->tx_queues[i] = NULL;
        }
        for (i = 0; i < lif->nrxqcqs; i++) {
-               ionic_dev_rx_queue_release(lif->eth_dev->data->rx_queues[i]);
+               ionic_dev_rx_queue_release(lif->eth_dev, i);
                lif->eth_dev->data->rx_queues[i] = NULL;
        }
 }
@@ -1605,17 +1608,18 @@ int
 ionic_lif_init(struct ionic_lif *lif)
 {
        struct ionic_dev *idev = &lif->adapter->idev;
-       struct ionic_q_init_comp comp;
+       struct ionic_lif_init_comp comp;
        int err;
 
        memset(&lif->stats_base, 0, sizeof(lif->stats_base));
 
        ionic_dev_cmd_lif_init(idev, lif->info_pa);
        err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
-       ionic_dev_cmd_comp(idev, &comp);
        if (err)
                return err;
 
+       ionic_dev_cmd_comp(idev, &comp);
+
        lif->hw_index = rte_cpu_to_le_16(comp.hw_index);
 
        err = ionic_lif_adminq_init(lif);
@@ -1684,12 +1688,12 @@ ionic_lif_configure_vlan_offload(struct ionic_lif *lif, int mask)
 
        /*
         * IONIC_ETH_HW_VLAN_RX_FILTER cannot be turned off, so
-        * set DEV_RX_OFFLOAD_VLAN_FILTER and ignore ETH_VLAN_FILTER_MASK
+        * set RTE_ETH_RX_OFFLOAD_VLAN_FILTER and ignore RTE_ETH_VLAN_FILTER_MASK
         */
-       rxmode->offloads |= DEV_RX_OFFLOAD_VLAN_FILTER;
+       rxmode->offloads |= RTE_ETH_RX_OFFLOAD_VLAN_FILTER;
 
-       if (mask & ETH_VLAN_STRIP_MASK) {
-               if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
+       if (mask & RTE_ETH_VLAN_STRIP_MASK) {
+               if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
                        lif->features |= IONIC_ETH_HW_VLAN_RX_STRIP;
                else
                        lif->features &= ~IONIC_ETH_HW_VLAN_RX_STRIP;
@@ -1729,19 +1733,19 @@ ionic_lif_configure(struct ionic_lif *lif)
        /*
         * NB: While it is true that RSS_HASH is always enabled on ionic,
         *     setting this flag unconditionally causes problems in DTS.
-        * rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
+        * rxmode->offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
         */
 
        /* RX per-port */
 
-       if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM ||
-           rxmode->offloads & DEV_RX_OFFLOAD_UDP_CKSUM ||
-           rxmode->offloads & DEV_RX_OFFLOAD_TCP_CKSUM)
+       if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_IPV4_CKSUM ||
+           rxmode->offloads & RTE_ETH_RX_OFFLOAD_UDP_CKSUM ||
+           rxmode->offloads & RTE_ETH_RX_OFFLOAD_TCP_CKSUM)
                lif->features |= IONIC_ETH_HW_RX_CSUM;
        else
                lif->features &= ~IONIC_ETH_HW_RX_CSUM;
 
-       if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER) {
+       if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_SCATTER) {
                lif->features |= IONIC_ETH_HW_RX_SG;
                lif->eth_dev->data->scattered_rx = 1;
        } else {
@@ -1750,30 +1754,30 @@ ionic_lif_configure(struct ionic_lif *lif)
        }
 
        /* Covers VLAN_STRIP */
-       ionic_lif_configure_vlan_offload(lif, ETH_VLAN_STRIP_MASK);
+       ionic_lif_configure_vlan_offload(lif, RTE_ETH_VLAN_STRIP_MASK);
 
        /* TX per-port */
 
-       if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
-           txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
-           txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM ||
-           txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
-           txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
+       if (txmode->offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM ||
+           txmode->offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM ||
+           txmode->offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM ||
+           txmode->offloads & RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
+           txmode->offloads & RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM)
                lif->features |= IONIC_ETH_HW_TX_CSUM;
        else
                lif->features &= ~IONIC_ETH_HW_TX_CSUM;
 
-       if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT)
+       if (txmode->offloads & RTE_ETH_TX_OFFLOAD_VLAN_INSERT)
                lif->features |= IONIC_ETH_HW_VLAN_TX_TAG;
        else
                lif->features &= ~IONIC_ETH_HW_VLAN_TX_TAG;
 
-       if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
+       if (txmode->offloads & RTE_ETH_TX_OFFLOAD_MULTI_SEGS)
                lif->features |= IONIC_ETH_HW_TX_SG;
        else
                lif->features &= ~IONIC_ETH_HW_TX_SG;
 
-       if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) {
+       if (txmode->offloads & RTE_ETH_TX_OFFLOAD_TCP_TSO) {
                lif->features |= IONIC_ETH_HW_TSO;
                lif->features |= IONIC_ETH_HW_TSO_IPV6;
                lif->features |= IONIC_ETH_HW_TSO_ECN;