net/ena: update version to 2.0.1

[dpdk.git] / drivers / net / ipn3ke / ipn3ke_ethdev.c

diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.c b/drivers/net/ipn3ke/ipn3ke_ethdev.c
index 508ea01..c226d63 100644 (file)
--- a/drivers/net/ipn3ke/ipn3ke_ethdev.c
+++ b/drivers/net/ipn3ke/ipn3ke_ethdev.c
@@ -21,6 +21,7 @@
 #include <ifpga_logs.h>
 
 #include "ipn3ke_rawdev_api.h"
+#include "ipn3ke_flow.h"
 #include "ipn3ke_logs.h"
 #include "ipn3ke_ethdev.h"
 
@@ -47,7 +48,6 @@ ipn3ke_indirect_read(struct ipn3ke_hw *hw, uint32_t *rd_data,
        if (eth_group_sel != 0 && eth_group_sel != 1)
                return -1;
 
-       addr &= 0x3FF;
        target_addr = addr | dev_sel << 17;
 
        indirect_value = RCMD | target_addr << 32;
@@ -85,7 +85,6 @@ ipn3ke_indirect_write(struct ipn3ke_hw *hw, uint32_t wr_data,
        if (eth_group_sel != 0 && eth_group_sel != 1)
                return -1;
 
-       addr &= 0x3FF;
        target_addr = addr | dev_sel << 17;
 
        indirect_value = WCMD | target_addr << 32 | wr_data;
@@ -190,6 +189,26 @@ ipn3ke_hw_cap_init(struct ipn3ke_hw *hw)
                        0, 0xFFFFF);
 }
 
+static int
+ipn3ke_vbng_init_done(struct ipn3ke_hw *hw)
+{
+       uint32_t timeout = 10000;
+       while (timeout > 0) {
+               if (IPN3KE_READ_REG(hw, IPN3KE_VBNG_INIT_STS)
+                       == IPN3KE_VBNG_INIT_DONE)
+                       break;
+               rte_delay_us(1000);
+               timeout--;
+       }
+
+       if (!timeout) {
+               IPN3KE_AFU_PMD_ERR("IPN3KE vBNG INIT timeout.\n");
+               return -1;
+       }
+
+       return 0;
+}
+
 static int
 ipn3ke_hw_init(struct rte_afu_device *afu_dev,
        struct ipn3ke_hw *hw)
@@ -222,15 +241,24 @@ ipn3ke_hw_init(struct rte_afu_device *afu_dev,
                                "LineSideMACType", &mac_type);
        hw->retimer.mac_type = (int)mac_type;
 
+       IPN3KE_AFU_PMD_DEBUG("UPL_version is 0x%x\n", IPN3KE_READ_REG(hw, 0));
+
        if (afu_dev->id.uuid.uuid_low == IPN3KE_UUID_VBNG_LOW &&
                afu_dev->id.uuid.uuid_high == IPN3KE_UUID_VBNG_HIGH) {
+               /* After power on, wait until init done */
+               if (ipn3ke_vbng_init_done(hw))
+                       return -1;
+
                ipn3ke_hw_cap_init(hw);
-               IPN3KE_AFU_PMD_DEBUG("UPL_version is 0x%x\n",
-                       IPN3KE_READ_REG(hw, 0));
 
-               /* Reset FPGA IP */
+               /* Reset vBNG IP */
                IPN3KE_WRITE_REG(hw, IPN3KE_CTRL_RESET, 1);
+               rte_delay_us(10);
                IPN3KE_WRITE_REG(hw, IPN3KE_CTRL_RESET, 0);
+
+               /* After reset, wait until init done */
+               if (ipn3ke_vbng_init_done(hw))
+                       return -1;
        }
 
        if (hw->retimer.mac_type == IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI) {
@@ -245,11 +273,33 @@ ipn3ke_hw_init(struct rte_afu_device *afu_dev,
                        /* Enable the RX path */
                        ipn3ke_xmac_rx_enable(hw, i, 1);
 
-                       /* Clear all TX statistics counters */
-                       ipn3ke_xmac_tx_clr_stcs(hw, i, 1);
+                       /* Clear NIC side TX statistics counters */
+                       ipn3ke_xmac_tx_clr_10G_stcs(hw, i, 1);
+
+                       /* Clear NIC side RX statistics counters */
+                       ipn3ke_xmac_rx_clr_10G_stcs(hw, i, 1);
 
-                       /* Clear all RX statistics counters */
-                       ipn3ke_xmac_rx_clr_stcs(hw, i, 1);
+                       /* Clear line side TX statistics counters */
+                       ipn3ke_xmac_tx_clr_10G_stcs(hw, i, 0);
+
+                       /* Clear line RX statistics counters */
+                       ipn3ke_xmac_rx_clr_10G_stcs(hw, i, 0);
+               }
+       } else if (hw->retimer.mac_type ==
+                       IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI) {
+               /* Enable inter connect channel */
+               for (i = 0; i < hw->port_num; i++) {
+                       /* Clear NIC side TX statistics counters */
+                       ipn3ke_xmac_tx_clr_25G_stcs(hw, i, 1);
+
+                       /* Clear NIC side RX statistics counters */
+                       ipn3ke_xmac_rx_clr_25G_stcs(hw, i, 1);
+
+                       /* Clear line side TX statistics counters */
+                       ipn3ke_xmac_tx_clr_25G_stcs(hw, i, 0);
+
+                       /* Clear line side RX statistics counters */
+                       ipn3ke_xmac_rx_clr_25G_stcs(hw, i, 0);
                }
        }
 
@@ -266,6 +316,10 @@ ipn3ke_hw_init(struct rte_afu_device *afu_dev,
                if (ret)
                        return ret;
                hw->tm_hw_enable = 1;
+
+               ret = ipn3ke_flow_init(hw);
+               if (ret)
+                       return ret;
                hw->flow_hw_enable = 1;
        }
 
@@ -288,11 +342,32 @@ ipn3ke_hw_uninit(struct ipn3ke_hw *hw)
                        /* Disable the RX path */
                        ipn3ke_xmac_rx_disable(hw, i, 1);
 
-                       /* Clear all TX statistics counters */
-                       ipn3ke_xmac_tx_clr_stcs(hw, i, 1);
+                       /* Clear NIC side TX statistics counters */
+                       ipn3ke_xmac_tx_clr_10G_stcs(hw, i, 1);
+
+                       /* Clear NIC side RX statistics counters */
+                       ipn3ke_xmac_rx_clr_10G_stcs(hw, i, 1);
+
+                       /* Clear line side TX statistics counters */
+                       ipn3ke_xmac_tx_clr_10G_stcs(hw, i, 0);
+
+                       /* Clear line side RX statistics counters */
+                       ipn3ke_xmac_rx_clr_10G_stcs(hw, i, 0);
+               }
+       } else if (hw->retimer.mac_type ==
+                       IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI) {
+               for (i = 0; i < hw->port_num; i++) {
+                       /* Clear NIC side TX statistics counters */
+                       ipn3ke_xmac_tx_clr_25G_stcs(hw, i, 1);
+
+                       /* Clear NIC side RX statistics counters */
+                       ipn3ke_xmac_rx_clr_25G_stcs(hw, i, 1);
+
+                       /* Clear line side TX statistics counters */
+                       ipn3ke_xmac_tx_clr_25G_stcs(hw, i, 0);
 
-                       /* Clear all RX statistics counters */
-                       ipn3ke_xmac_rx_clr_stcs(hw, i, 1);
+                       /* Clear line side RX statistics counters */
+                       ipn3ke_xmac_rx_clr_25G_stcs(hw, i, 0);
                }
        }
 }