-/*******************************************************************************
-
-Copyright (c) 2001-2015, Intel Corporation
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
- this list of conditions and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
-
- 3. Neither the name of the Intel Corporation nor the names of its
- contributors may be used to endorse or promote products derived from
- this software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGE.
-
-***************************************************************************/
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2001-2020 Intel Corporation
+ */
#include "ixgbe_type.h"
#include "ixgbe_82599.h"
}
/**
- * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
- * @hw: pointer to hardware structure
+ * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
+ * @hw: pointer to hardware structure
*
- * Initialize any function pointers that were not able to be
- * set during init_shared_code because the PHY/SFP type was
- * not known. Perform the SFP init if necessary.
+ * Initialize any function pointers that were not able to be
+ * set during init_shared_code because the PHY/SFP type was
+ * not known. Perform the SFP init if necessary.
*
**/
s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
}
/**
- * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read
- * @hw: pointer to hardware structure
- * @locked: Return the if we locked for this read.
- * @reg_val: Value we read from AUTOC
+ * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read
+ * @hw: pointer to hardware structure
+ * @locked: Return the if we locked for this read.
+ * @reg_val: Value we read from AUTOC
*
- * For this part (82599) we need to wrap read-modify-writes with a possible
- * FW/SW lock. It is assumed this lock will be freed with the next
- * prot_autoc_write_82599().
+ * For this part (82599) we need to wrap read-modify-writes with a possible
+ * FW/SW lock. It is assumed this lock will be freed with the next
+ * prot_autoc_write_82599().
*/
s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
{
/**
* prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write
* @hw: pointer to hardware structure
- * @reg_val: value to write to AUTOC
+ * @autoc: value to write to AUTOC
* @locked: bool to indicate whether the SW/FW lock was already taken by
- * previous proc_autoc_read_82599.
+ * previous proc_autoc_read_82599.
*
* This part (82599) may need to hold the SW/FW lock around all writes to
* AUTOC. Likewise after a write we need to do a pipeline reset.
}
/**
- * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
- * @hw: pointer to hardware structure
+ * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
+ * @hw: pointer to hardware structure
*
- * Initialize the function pointers and assign the MAC type for 82599.
- * Does not touch the hardware.
+ * Initialize the function pointers and assign the MAC type for 82599.
+ * Does not touch the hardware.
**/
s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
- mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
- IXGBE_FWSM_MODE_MASK) ? true : false;
+ mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw))
+ & IXGBE_FWSM_MODE_MASK);
hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
}
/**
- * ixgbe_get_link_capabilities_82599 - Determines link capabilities
- * @hw: pointer to hardware structure
- * @speed: pointer to link speed
- * @autoneg: true when autoneg or autotry is enabled
+ * ixgbe_get_link_capabilities_82599 - Determines link capabilities
+ * @hw: pointer to hardware structure
+ * @speed: pointer to link speed
+ * @autoneg: true when autoneg or autotry is enabled
*
- * Determines the link capabilities by reading the AUTOC register.
+ * Determines the link capabilities by reading the AUTOC register.
**/
s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
ixgbe_link_speed *speed,
/* Check if 1G SFP module. */
if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
+ hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core0 ||
+ hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core1 ||
hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
}
/**
- * ixgbe_get_media_type_82599 - Get media type
- * @hw: pointer to hardware structure
+ * ixgbe_get_media_type_82599 - Get media type
+ * @hw: pointer to hardware structure
*
- * Returns the media type (fiber, copper, backplane)
+ * Returns the media type (fiber, copper, backplane)
**/
enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
{
case IXGBE_DEV_ID_82599_T3_LOM:
media_type = ixgbe_media_type_copper;
break;
- case IXGBE_DEV_ID_82599_LS:
- media_type = ixgbe_media_type_fiber_lco;
- break;
case IXGBE_DEV_ID_82599_QSFP_SF_QP:
media_type = ixgbe_media_type_fiber_qsfp;
break;
}
/**
- * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
- * @hw: pointer to hardware structure
+ * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
+ * @hw: pointer to hardware structure
*
- * Disables link during D3 power down sequence.
+ * Disables link during D3 power down sequence.
*
**/
void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
}
/**
- * ixgbe_start_mac_link_82599 - Setup MAC link settings
- * @hw: pointer to hardware structure
- * @autoneg_wait_to_complete: true when waiting for completion is needed
+ * ixgbe_start_mac_link_82599 - Setup MAC link settings
+ * @hw: pointer to hardware structure
+ * @autoneg_wait_to_complete: true when waiting for completion is needed
*
- * Configures link settings based on values in the ixgbe_hw struct.
- * Restarts the link. Performs autonegotiation if needed.
+ * Configures link settings based on values in the ixgbe_hw struct.
+ * Restarts the link. Performs autonegotiation if needed.
**/
s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
bool autoneg_wait_to_complete)
}
/**
- * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
- * @hw: pointer to hardware structure
+ * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
+ * @hw: pointer to hardware structure
*
- * The base drivers may require better control over SFP+ module
- * PHY states. This includes selectively shutting down the Tx
- * laser on the PHY, effectively halting physical link.
+ * The base drivers may require better control over SFP+ module
+ * PHY states. This includes selectively shutting down the Tx
+ * laser on the PHY, effectively halting physical link.
**/
void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
{
}
/**
- * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
- * @hw: pointer to hardware structure
+ * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
+ * @hw: pointer to hardware structure
*
- * The base drivers may require better control over SFP+ module
- * PHY states. This includes selectively turning on the Tx
- * laser on the PHY, effectively starting physical link.
+ * The base drivers may require better control over SFP+ module
+ * PHY states. This includes selectively turning on the Tx
+ * laser on the PHY, effectively starting physical link.
**/
void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
{
}
/**
- * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
- * @hw: pointer to hardware structure
+ * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
+ * @hw: pointer to hardware structure
*
- * When the driver changes the link speeds that it can support,
- * it sets autotry_restart to true to indicate that we need to
- * initiate a new autotry session with the link partner. To do
- * so, we set the speed then disable and re-enable the Tx laser, to
- * alert the link partner that it also needs to restart autotry on its
- * end. This is consistent with true clause 37 autoneg, which also
- * involves a loss of signal.
+ * When the driver changes the link speeds that it can support,
+ * it sets autotry_restart to true to indicate that we need to
+ * initiate a new autotry session with the link partner. To do
+ * so, we set the speed then disable and re-enable the Tx laser, to
+ * alert the link partner that it also needs to restart autotry on its
+ * end. This is consistent with true clause 37 autoneg, which also
+ * involves a loss of signal.
**/
void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
{
}
/**
- * ixgbe_set_hard_rate_select_speed - Set module link speed
- * @hw: pointer to hardware structure
- * @speed: link speed to set
+ * ixgbe_set_hard_rate_select_speed - Set module link speed
+ * @hw: pointer to hardware structure
+ * @speed: link speed to set
*
- * Set module link speed via RS0/RS1 rate select pins.
+ * Set module link speed via RS0/RS1 rate select pins.
*/
void ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw,
ixgbe_link_speed speed)
}
/**
- * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
- * @hw: pointer to hardware structure
- * @speed: new link speed
- * @autoneg_wait_to_complete: true when waiting for completion is needed
+ * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
+ * @hw: pointer to hardware structure
+ * @speed: new link speed
+ * @autoneg_wait_to_complete: true when waiting for completion is needed
*
- * Implements the Intel SmartSpeed algorithm.
+ * Implements the Intel SmartSpeed algorithm.
**/
s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
ixgbe_link_speed speed,
}
/**
- * ixgbe_setup_mac_link_82599 - Set MAC link speed
- * @hw: pointer to hardware structure
- * @speed: new link speed
- * @autoneg_wait_to_complete: true when waiting for completion is needed
+ * ixgbe_setup_mac_link_82599 - Set MAC link speed
+ * @hw: pointer to hardware structure
+ * @speed: new link speed
+ * @autoneg_wait_to_complete: true when waiting for completion is needed
*
- * Set the link speed in the AUTOC register and restarts link.
+ * Set the link speed in the AUTOC register and restarts link.
**/
s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
ixgbe_link_speed speed,
}
/**
- * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
- * @hw: pointer to hardware structure
- * @speed: new link speed
- * @autoneg_wait_to_complete: true if waiting is needed to complete
+ * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
+ * @hw: pointer to hardware structure
+ * @speed: new link speed
+ * @autoneg_wait_to_complete: true if waiting is needed to complete
*
- * Restarts link on PHY and MAC based on settings passed in.
+ * Restarts link on PHY and MAC based on settings passed in.
**/
STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
ixgbe_link_speed speed,
}
/**
- * ixgbe_reset_hw_82599 - Perform hardware reset
- * @hw: pointer to hardware structure
+ * ixgbe_reset_hw_82599 - Perform hardware reset
+ * @hw: pointer to hardware structure
*
- * Resets the hardware by resetting the transmit and receive units, masks
- * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
- * reset.
+ * Resets the hardware by resetting the transmit and receive units, masks
+ * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
+ * reset.
**/
s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
{
/* Add the SAN MAC address to the RAR only if it's a valid address */
if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
- hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
- hw->mac.san_addr, 0, IXGBE_RAH_AV);
-
/* Save the SAN MAC RAR index */
hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
+ hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
+ hw->mac.san_addr, 0, IXGBE_RAH_AV);
+
+ /* clear VMDq pool/queue selection for this RAR */
+ hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
+ IXGBE_CLEAR_VMDQ_ALL);
+
/* Reserve the last RAR for the SAN MAC address */
hw->mac.num_rar_entries--;
}
}
/**
- * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
- * @hw: pointer to hardware structure
+ * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
+ * @hw: pointer to hardware structure
**/
s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
{
}
/**
- * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
- * @hw: pointer to hardware structure
- * @fdirctrl: value to write to flow director control register
+ * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
+ * @hw: pointer to hardware structure
+ * @fdirctrl: value to write to flow director control register
**/
STATIC void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
{
}
/**
- * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
- * @hw: pointer to hardware structure
- * @fdirctrl: value to write to flow director control register, initially
+ * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
+ * @hw: pointer to hardware structure
+ * @fdirctrl: value to write to flow director control register, initially
* contains just the value of the Rx packet buffer allocation
**/
s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
}
/**
- * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
- * @hw: pointer to hardware structure
- * @fdirctrl: value to write to flow director control register, initially
+ * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
+ * @hw: pointer to hardware structure
+ * @fdirctrl: value to write to flow director control register, initially
* contains just the value of the Rx packet buffer allocation
- * @cloud_mode: true - cloud mode, false - other mode
+ * @cloud_mode: true - cloud mode, false - other mode
**/
s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
bool cloud_mode)
{
+ UNREFERENCED_1PARAMETER(cloud_mode);
DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
/*
(0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
(0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
(4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
- if ((hw->mac.type == ixgbe_mac_X550) ||
- (hw->mac.type == ixgbe_mac_X550EM_x))
- fdirctrl |= IXGBE_FDIRCTRL_DROP_NO_MATCH;
if (cloud_mode)
fdirctrl |=(IXGBE_FDIRCTRL_FILTERMODE_CLOUD <<
}
/**
- * ixgbe_set_fdir_drop_queue_82599 - Set Flow Director drop queue
- * @hw: pointer to hardware structure
- * @dropqueue: Rx queue index used for the dropped packets
+ * ixgbe_set_fdir_drop_queue_82599 - Set Flow Director drop queue
+ * @hw: pointer to hardware structure
+ * @dropqueue: Rx queue index used for the dropped packets
**/
void ixgbe_set_fdir_drop_queue_82599(struct ixgbe_hw *hw, u8 dropqueue)
{
/* Set drop queue */
fdirctrl |= (dropqueue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
if ((hw->mac.type == ixgbe_mac_X550) ||
- (hw->mac.type == ixgbe_mac_X550EM_x))
+ (hw->mac.type == ixgbe_mac_X550EM_x) ||
+ (hw->mac.type == ixgbe_mac_X550EM_a))
fdirctrl |= IXGBE_FDIRCTRL_DROP_NO_MATCH;
IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
} while (0)
/**
- * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
- * @stream: input bitstream to compute the hash on
+ * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
+ * @input: input bitstream to compute the hash on
+ * @common: compressed common input dword
*
- * This function is almost identical to the function above but contains
- * several optimizations such as unwinding all of the loops, letting the
- * compiler work out all of the conditional ifs since the keys are static
- * defines, and computing two keys at once since the hashed dword stream
- * will be the same for both keys.
+ * This function is almost identical to the function above but contains
+ * several optimizations such as unwinding all of the loops, letting the
+ * compiler work out all of the conditional ifs since the keys are static
+ * defines, and computing two keys at once since the hashed dword stream
+ * will be the same for both keys.
**/
u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
union ixgbe_atr_hash_dword common)
}
/**
- * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
- * @hw: pointer to hardware structure
- * @input: unique input dword
- * @common: compressed common input dword
- * @queue: queue index to direct traffic to
+ * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
+ * @hw: pointer to hardware structure
+ * @input: unique input dword
+ * @common: compressed common input dword
+ * @queue: queue index to direct traffic to
*
* Note that the tunnel bit in input must not be set when the hardware
* tunneling support does not exist.
* is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
*/
fdirhashcmd = (u64)fdircmd << 32;
- fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
+ fdirhashcmd |= (u64)ixgbe_atr_compute_sig_hash_82599(input, common);
IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
} while (0)
/**
- * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
- * @atr_input: input bitstream to compute the hash on
- * @input_mask: mask for the input bitstream
+ * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
+ * @input: input bitstream to compute the hash on
+ * @input_mask: mask for the input bitstream
*
- * This function serves two main purposes. First it applies the input_mask
- * to the atr_input resulting in a cleaned up atr_input data stream.
- * Secondly it computes the hash and stores it in the bkt_hash field at
- * the end of the input byte stream. This way it will be available for
- * future use without needing to recompute the hash.
+ * This function serves two main purposes. First it applies the input_mask
+ * to the atr_input resulting in a cleaned up atr_input data stream.
+ * Secondly it computes the hash and stores it in the bkt_hash field at
+ * the end of the input byte stream. This way it will be available for
+ * future use without needing to recompute the hash.
**/
void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
union ixgbe_atr_input *input_mask)
}
/**
- * ixgbe_get_fdirtcpm_82599 - generate a TCP port from atr_input_masks
- * @input_mask: mask to be bit swapped
+ * ixgbe_get_fdirtcpm_82599 - generate a TCP port from atr_input_masks
+ * @input_mask: mask to be bit swapped
*
- * The source and destination port masks for flow director are bit swapped
- * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
- * generate a correctly swapped value we need to bit swap the mask and that
- * is what is accomplished by this function.
+ * The source and destination port masks for flow director are bit swapped
+ * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
+ * generate a correctly swapped value we need to bit swap the mask and that
+ * is what is accomplished by this function.
**/
STATIC u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
{
u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
- mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
+ mask |= (u32)IXGBE_NTOHS(input_mask->formatted.src_port);
mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
u32 fdirm = IXGBE_FDIRM_DIPv6;
u32 fdirtcpm;
u32 fdirip6m;
+ UNREFERENCED_1PARAMETER(cloud_mode);
DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
/*
switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
case 0x0000:
- /* mask VLAN ID, fall through to mask VLAN priority */
+ /* mask VLAN ID */
fdirm |= IXGBE_FDIRM_VLANID;
+ /* fall through */
case 0x0FFF:
/* mask VLAN priority */
fdirm |= IXGBE_FDIRM_VLANP;
break;
case 0xE000:
- /* mask VLAN ID only, fall through */
+ /* mask VLAN ID only */
fdirm |= IXGBE_FDIRM_VLANID;
+ /* fall through */
case 0xEFFF:
/* no VLAN fields masked */
break;
switch (input_mask->formatted.flex_bytes & 0xFFFF) {
case 0x0000:
- /* Mask Flex Bytes, fall through */
+ /* Mask Flex Bytes */
fdirm |= IXGBE_FDIRM_FLEX;
+ /* fall through */
case 0xFFFF:
break;
default:
}
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m);
- /* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSIP4M and
- * FDIRDIP4M in cloud mode to allow L3/L3 packets to
- * tunnel.
+ /* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSCTPM,
+ * FDIRSIP4M and FDIRDIP4M in cloud mode to allow
+ * L3/L3 packets to tunnel.
*/
IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF);
IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF);
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF);
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF);
+ switch (hw->mac.type) {
+ case ixgbe_mac_X550:
+ case ixgbe_mac_X550EM_x:
+ case ixgbe_mac_X550EM_a:
+ IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF);
+ break;
+ default:
+ break;
+ }
}
/* Now mask VM pool and destination IPv6 - bits 5 and 2 */
switch (hw->mac.type) {
case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x:
+ case ixgbe_mac_X550EM_a:
IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);
break;
default:
~input_mask->formatted.src_ip[0]);
IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
~input_mask->formatted.dst_ip[0]);
+ IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, 0xFFFFFFFF);
}
return IXGBE_SUCCESS;
}
u32 addr_low, addr_high;
u32 cloud_type = 0;
s32 err;
+ UNREFERENCED_1PARAMETER(cloud_mode);
DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
if (!cloud_mode) {
/* record source and destination port (little-endian)*/
fdirport = IXGBE_NTOHS(input->formatted.dst_port);
fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
- fdirport |= IXGBE_NTOHS(input->formatted.src_port);
+ fdirport |= (u32)IXGBE_NTOHS(input->formatted.src_port);
IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
}
/* record VLAN (little-endian) and flex_bytes(big-endian) */
fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
- fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
+ fdirvlan |= (u32)IXGBE_NTOHS(input->formatted.vlan_id);
IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
if (cloud_mode) {
}
/**
- * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
- * @hw: pointer to hardware structure
- * @input: input bitstream
- * @input_mask: mask for the input bitstream
- * @soft_id: software index for the filters
- * @queue: queue index to direct traffic to
+ * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
+ * @hw: pointer to hardware structure
+ * @input: input bitstream
+ * @input_mask: mask for the input bitstream
+ * @soft_id: software index for the filters
+ * @queue: queue index to direct traffic to
+ * @cloud_mode: unused
*
- * Note that the caller to this function must lock before calling, since the
- * hardware writes must be protected from one another.
+ * Note that the caller to this function must lock before calling, since the
+ * hardware writes must be protected from one another.
**/
s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
union ixgbe_atr_input *input,
u16 soft_id, u8 queue, bool cloud_mode)
{
s32 err = IXGBE_ERR_CONFIG;
+ UNREFERENCED_1PARAMETER(cloud_mode);
DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
DEBUGOUT(" Error on src/dst port\n");
return IXGBE_ERR_CONFIG;
}
+ /* fall through */
case IXGBE_ATR_FLOW_TYPE_TCPV4:
case IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4:
case IXGBE_ATR_FLOW_TYPE_UDPV4:
}
/**
- * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
- * @hw: pointer to hardware structure
- * @reg: analog register to read
- * @val: read value
+ * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
+ * @hw: pointer to hardware structure
+ * @reg: analog register to read
+ * @val: read value
*
- * Performs read operation to Omer analog register specified.
+ * Performs read operation to Omer analog register specified.
**/
s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
{
}
/**
- * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
- * @hw: pointer to hardware structure
- * @reg: atlas register to write
- * @val: value to write
+ * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
+ * @hw: pointer to hardware structure
+ * @reg: atlas register to write
+ * @val: value to write
*
- * Performs write operation to Omer analog register specified.
+ * Performs write operation to Omer analog register specified.
**/
s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
{
}
/**
- * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
- * @hw: pointer to hardware structure
+ * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
+ * @hw: pointer to hardware structure
*
- * Starts the hardware using the generic start_hw function
- * and the generation start_hw function.
- * Then performs revision-specific operations, if any.
+ * Starts the hardware using the generic start_hw function
+ * and the generation start_hw function.
+ * Then performs revision-specific operations, if any.
**/
s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
{
if (ret_val != IXGBE_SUCCESS)
goto out;
- ret_val = ixgbe_start_hw_gen2(hw);
- if (ret_val != IXGBE_SUCCESS)
- goto out;
+ ixgbe_start_hw_gen2(hw);
/* We need to run link autotry after the driver loads */
hw->mac.autotry_restart = true;
}
/**
- * ixgbe_identify_phy_82599 - Get physical layer module
- * @hw: pointer to hardware structure
+ * ixgbe_identify_phy_82599 - Get physical layer module
+ * @hw: pointer to hardware structure
*
- * Determines the physical layer module found on the current adapter.
- * If PHY already detected, maintains current PHY type in hw struct,
- * otherwise executes the PHY detection routine.
+ * Determines the physical layer module found on the current adapter.
+ * If PHY already detected, maintains current PHY type in hw struct,
+ * otherwise executes the PHY detection routine.
**/
s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
{
}
/**
- * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
- * @hw: pointer to hardware structure
+ * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
+ * @hw: pointer to hardware structure
*
- * Determines physical layer capabilities of the current configuration.
+ * Determines physical layer capabilities of the current configuration.
**/
-u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
+u64 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
{
- u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
+ u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
}
/**
- * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
- * @hw: pointer to hardware structure
- * @regval: register value to write to RXCTRL
+ * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
+ * @hw: pointer to hardware structure
+ * @regval: register value to write to RXCTRL
*
- * Enables the Rx DMA unit for 82599
+ * Enables the Rx DMA unit for 82599
**/
s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
{
}
/**
- * ixgbe_verify_fw_version_82599 - verify FW version for 82599
- * @hw: pointer to hardware structure
+ * ixgbe_verify_fw_version_82599 - verify FW version for 82599
+ * @hw: pointer to hardware structure
*
- * Verifies that installed the firmware version is 0.6 or higher
- * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
+ * Verifies that installed the firmware version is 0.6 or higher
+ * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
*
- * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
- * if the FW version is not supported.
+ * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
+ * if the FW version is not supported.
**/
STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
{
}
/**
- * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
- * @hw: pointer to hardware structure
+ * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
+ * @hw: pointer to hardware structure
*
- * Returns true if the LESM FW module is present and enabled. Otherwise
- * returns false. Smart Speed must be disabled if LESM FW module is enabled.
+ * Returns true if the LESM FW module is present and enabled. Otherwise
+ * returns false. Smart Speed must be disabled if LESM FW module is enabled.
**/
bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
{
}
/**
- * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
- * fastest available method
+ * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
+ * fastest available method
*
- * @hw: pointer to hardware structure
- * @offset: offset of word in EEPROM to read
- * @words: number of words
- * @data: word(s) read from the EEPROM
+ * @hw: pointer to hardware structure
+ * @offset: offset of word in EEPROM to read
+ * @words: number of words
+ * @data: word(s) read from the EEPROM
*
- * Retrieves 16 bit word(s) read from EEPROM
+ * Retrieves 16 bit word(s) read from EEPROM
**/
STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
u16 words, u16 *data)
}
/**
- * ixgbe_read_eeprom_82599 - Read EEPROM word using
- * fastest available method
+ * ixgbe_read_eeprom_82599 - Read EEPROM word using
+ * fastest available method
*
- * @hw: pointer to hardware structure
- * @offset: offset of word in the EEPROM to read
- * @data: word read from the EEPROM
+ * @hw: pointer to hardware structure
+ * @offset: offset of word in the EEPROM to read
+ * @data: word read from the EEPROM
*
- * Reads a 16 bit word from the EEPROM
+ * Reads a 16 bit word from the EEPROM
**/
STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
u16 offset, u16 *data)
/**
* ixgbe_reset_pipeline_82599 - perform pipeline reset
*
- * @hw: pointer to hardware structure
+ * @hw: pointer to hardware structure
*
* Reset pipeline by asserting Restart_AN together with LMS change to ensure
* full pipeline reset. This function assumes the SW/FW lock is held.
}
/**
- * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
- * @hw: pointer to hardware structure
- * @byte_offset: byte offset to read
- * @data: value read
+ * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
+ * @hw: pointer to hardware structure
+ * @byte_offset: byte offset to read
+ * @dev_addr: address to read from
+ * @data: value read
*
- * Performs byte read operation to SFP module's EEPROM over I2C interface at
- * a specified device address.
+ * Performs byte read operation to SFP module's EEPROM over I2C interface at
+ * a specified device address.
**/
STATIC s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 *data)
}
/**
- * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
- * @hw: pointer to hardware structure
- * @byte_offset: byte offset to write
- * @data: value to write
+ * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
+ * @hw: pointer to hardware structure
+ * @byte_offset: byte offset to write
+ * @dev_addr: address to read from
+ * @data: value to write
*
- * Performs byte write operation to SFP module's EEPROM over I2C interface at
- * a specified device address.
+ * Performs byte write operation to SFP module's EEPROM over I2C interface at
+ * a specified device address.
**/
STATIC s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 data)
git.droids-corp.org / dpdk.git / blobdiff