net/mlx4: enhance header files comments

[dpdk.git] / drivers / net / ixgbe / base / ixgbe_82599.c

diff --git a/drivers/net/ixgbe/base/ixgbe_82599.c b/drivers/net/ixgbe/base/ixgbe_82599.c
index 154c1f1..d9d11a8 100644 (file)
--- a/drivers/net/ixgbe/base/ixgbe_82599.c
+++ b/drivers/net/ixgbe/base/ixgbe_82599.c
@@ -1176,12 +1176,16 @@ mac_reset_top:
 
        /* Add the SAN MAC address to the RAR only if it's a valid address */
        if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
-               hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
-                                   hw->mac.san_addr, 0, IXGBE_RAH_AV);
-
                /* Save the SAN MAC RAR index */
                hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
 
+               hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
+                                   hw->mac.san_addr, 0, IXGBE_RAH_AV);
+
+               /* clear VMDq pool/queue selection for this RAR */
+               hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
+                                      IXGBE_CLEAR_VMDQ_ALL);
+
                /* Reserve the last RAR for the SAN MAC address */
                hw->mac.num_rar_entries--;
        }
@@ -1806,14 +1810,23 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
                }
                IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m);
 
-               /* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSIP4M and
-                * FDIRDIP4M in cloud mode to allow L3/L3 packets to
-                * tunnel.
+               /* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSCTPM,
+                * FDIRSIP4M and FDIRDIP4M in cloud mode to allow
+                * L3/L3 packets to tunnel.
                 */
                IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF);
                IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF);
                IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF);
                IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF);
+               switch (hw->mac.type) {
+               case ixgbe_mac_X550:
+               case ixgbe_mac_X550EM_x:
+               case ixgbe_mac_X550EM_a:
+                       IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF);
+                       break;
+               default:
+                       break;
+               }
        }
 
        /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
@@ -2156,9 +2169,9 @@ s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
  *
  *  Determines physical layer capabilities of the current configuration.
  **/
-u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
+u64 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
 {
-       u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
+       u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
        u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
        u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
        u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;