net/mlx4: enhance header files comments

[dpdk.git] / drivers / net / ixgbe / base / ixgbe_82599.c

diff --git a/drivers/net/ixgbe/base/ixgbe_82599.c b/drivers/net/ixgbe/base/ixgbe_82599.c
index 2318190..d9d11a8 100644 (file)
--- a/drivers/net/ixgbe/base/ixgbe_82599.c
+++ b/drivers/net/ixgbe/base/ixgbe_82599.c
@@ -1176,12 +1176,16 @@ mac_reset_top:
 
        /* Add the SAN MAC address to the RAR only if it's a valid address */
        if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
-               hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
-                                   hw->mac.san_addr, 0, IXGBE_RAH_AV);
-
                /* Save the SAN MAC RAR index */
                hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
 
+               hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
+                                   hw->mac.san_addr, 0, IXGBE_RAH_AV);
+
+               /* clear VMDq pool/queue selection for this RAR */
+               hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
+                                      IXGBE_CLEAR_VMDQ_ALL);
+
                /* Reserve the last RAR for the SAN MAC address */
                hw->mac.num_rar_entries--;
        }
@@ -1380,9 +1384,6 @@ s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
                    (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
                    (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
                    (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
-       if ((hw->mac.type == ixgbe_mac_X550) ||
-           (hw->mac.type == ixgbe_mac_X550EM_x))
-               fdirctrl |= IXGBE_FDIRCTRL_DROP_NO_MATCH;
 
        if (cloud_mode)
                fdirctrl |=(IXGBE_FDIRCTRL_FILTERMODE_CLOUD <<
@@ -1411,7 +1412,8 @@ void ixgbe_set_fdir_drop_queue_82599(struct ixgbe_hw *hw, u8 dropqueue)
        /* Set drop queue */
        fdirctrl |= (dropqueue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
        if ((hw->mac.type == ixgbe_mac_X550) ||
-           (hw->mac.type == ixgbe_mac_X550EM_x))
+           (hw->mac.type == ixgbe_mac_X550EM_x) ||
+           (hw->mac.type == ixgbe_mac_X550EM_a))
                fdirctrl |= IXGBE_FDIRCTRL_DROP_NO_MATCH;
 
        IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
@@ -1808,14 +1810,23 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
                }
                IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m);
 
-               /* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSIP4M and
-                * FDIRDIP4M in cloud mode to allow L3/L3 packets to
-                * tunnel.
+               /* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSCTPM,
+                * FDIRSIP4M and FDIRDIP4M in cloud mode to allow
+                * L3/L3 packets to tunnel.
                 */
                IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF);
                IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF);
                IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF);
                IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF);
+               switch (hw->mac.type) {
+               case ixgbe_mac_X550:
+               case ixgbe_mac_X550EM_x:
+               case ixgbe_mac_X550EM_a:
+                       IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF);
+                       break;
+               default:
+                       break;
+               }
        }
 
        /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
@@ -1833,6 +1844,7 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
                switch (hw->mac.type) {
                case ixgbe_mac_X550:
                case ixgbe_mac_X550EM_x:
+               case ixgbe_mac_X550EM_a:
                        IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);
                        break;
                default:
@@ -2157,9 +2169,9 @@ s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
  *
  *  Determines physical layer capabilities of the current configuration.
  **/
-u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
+u64 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
 {
-       u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
+       u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
        u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
        u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
        u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;