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ixgbe/base: abstract out link read/write
[dpdk.git] / drivers / net / ixgbe / base / ixgbe_common.c
diff --git a/drivers/net/ixgbe/base/ixgbe_common.c b/drivers/net/ixgbe/base/ixgbe_common.c
index 17db352..ec61408 100644 (file)
--- a/drivers/net/ixgbe/base/ixgbe_common.c
+++ b/drivers/net/ixgbe/base/ixgbe_common.c
@@ -69,7 +69,7 @@ s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
 {
        struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
        struct ixgbe_mac_info *mac = &hw->mac;
-       u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+       u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
 
        DEBUGFUNC("ixgbe_init_ops_generic");
 
@@ -185,6 +185,7 @@ bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
                case IXGBE_DEV_ID_X540T:
                case IXGBE_DEV_ID_X540T1:
                case IXGBE_DEV_ID_X550T:
+               case IXGBE_DEV_ID_X550T1:
                case IXGBE_DEV_ID_X550EM_X_10G_T:
                        supported = true;
                        break;
@@ -1034,7 +1035,7 @@ void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
        bus->lan_id = bus->func;
 
        /* check for a port swap */
-       reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
+       reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
        if (reg & IXGBE_FACTPS_LFS)
                bus->func ^= 0x1;
 }
@@ -1160,7 +1161,7 @@ s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
                 * Check for EEPROM present first.
                 * If not present leave as none
                 */
-               eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+               eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
                if (eec & IXGBE_EEC_PRES) {
                        eeprom->type = ixgbe_eeprom_spi;
 
@@ -1721,14 +1722,14 @@ STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
                status = IXGBE_ERR_SWFW_SYNC;
 
        if (status == IXGBE_SUCCESS) {
-               eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+               eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
 
                /* Request EEPROM Access */
                eec |= IXGBE_EEC_REQ;
-               IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+               IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
 
                for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
-                       eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+                       eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
                        if (eec & IXGBE_EEC_GNT)
                                break;
                        usec_delay(5);
@@ -1737,7 +1738,7 @@ STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
                /* Release if grant not acquired */
                if (!(eec & IXGBE_EEC_GNT)) {
                        eec &= ~IXGBE_EEC_REQ;
-                       IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+                       IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
                        DEBUGOUT("Could not acquire EEPROM grant\n");
 
                        hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
@@ -1748,7 +1749,7 @@ STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
                if (status == IXGBE_SUCCESS) {
                        /* Clear CS and SK */
                        eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
-                       IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+                       IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
                        IXGBE_WRITE_FLUSH(hw);
                        usec_delay(1);
                }
@@ -1778,7 +1779,7 @@ STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
                 * If the SMBI bit is 0 when we read it, then the bit will be
                 * set and we have the semaphore
                 */
-               swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
+               swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
                if (!(swsm & IXGBE_SWSM_SMBI)) {
                        status = IXGBE_SUCCESS;
                        break;
@@ -1803,7 +1804,7 @@ STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
                 * If the SMBI bit is 0 when we read it, then the bit will be
                 * set and we have the semaphore
                 */
-               swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
+               swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
                if (!(swsm & IXGBE_SWSM_SMBI))
                        status = IXGBE_SUCCESS;
        }
@@ -1811,17 +1812,17 @@ STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
        /* Now get the semaphore between SW/FW through the SWESMBI bit */
        if (status == IXGBE_SUCCESS) {
                for (i = 0; i < timeout; i++) {
-                       swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
+                       swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
 
                        /* Set the SW EEPROM semaphore bit to request access */
                        swsm |= IXGBE_SWSM_SWESMBI;
-                       IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
+                       IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
 
                        /*
                         * If we set the bit successfully then we got the
                         * semaphore.
                         */
-                       swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
+                       swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
                        if (swsm & IXGBE_SWSM_SWESMBI)
                                break;
 
@@ -1918,15 +1919,15 @@ STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
 
        DEBUGFUNC("ixgbe_standby_eeprom");
 
-       eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+       eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
 
        /* Toggle CS to flush commands */
        eec |= IXGBE_EEC_CS;
-       IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+       IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
        IXGBE_WRITE_FLUSH(hw);
        usec_delay(1);
        eec &= ~IXGBE_EEC_CS;
-       IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+       IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
        IXGBE_WRITE_FLUSH(hw);
        usec_delay(1);
 }
@@ -1946,7 +1947,7 @@ STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
 
        DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
 
-       eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+       eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
 
        /*
         * Mask is used to shift "count" bits of "data" out to the EEPROM
@@ -1967,7 +1968,7 @@ STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
                else
                        eec &= ~IXGBE_EEC_DI;
 
-               IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+               IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
                IXGBE_WRITE_FLUSH(hw);
 
                usec_delay(1);
@@ -1984,7 +1985,7 @@ STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
 
        /* We leave the "DI" bit set to "0" when we leave this routine. */
        eec &= ~IXGBE_EEC_DI;
-       IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+       IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
        IXGBE_WRITE_FLUSH(hw);
 }
 
@@ -2007,7 +2008,7 @@ STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
         * the value of the "DO" bit.  During this "shifting in" process the
         * "DI" bit should always be clear.
         */
-       eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+       eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
 
        eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
 
@@ -2015,7 +2016,7 @@ STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
                data = data << 1;
                ixgbe_raise_eeprom_clk(hw, &eec);
 
-               eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+               eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
 
                eec &= ~(IXGBE_EEC_DI);
                if (eec & IXGBE_EEC_DO)
@@ -2041,7 +2042,7 @@ STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
         * (setting the SK bit), then delay
         */
        *eec = *eec | IXGBE_EEC_SK;
-       IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
+       IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
        IXGBE_WRITE_FLUSH(hw);
        usec_delay(1);
 }
@@ -2060,7 +2061,7 @@ STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
         * delay
         */
        *eec = *eec & ~IXGBE_EEC_SK;
-       IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
+       IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec);
        IXGBE_WRITE_FLUSH(hw);
        usec_delay(1);
 }
@@ -2075,19 +2076,19 @@ STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw)
 
        DEBUGFUNC("ixgbe_release_eeprom");
 
-       eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+       eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
 
        eec |= IXGBE_EEC_CS;  /* Pull CS high */
        eec &= ~IXGBE_EEC_SK; /* Lower SCK */
 
-       IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+       IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
        IXGBE_WRITE_FLUSH(hw);
 
        usec_delay(1);
 
        /* Stop requesting EEPROM access */
        eec &= ~IXGBE_EEC_REQ;
-       IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+       IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec);
 
        hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 
@@ -2242,7 +2243,7 @@ s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
  *  ixgbe_validate_mac_addr - Validate MAC address
  *  @mac_addr: pointer to MAC address.
  *
- *  Tests a MAC address to ensure it is a valid Individual Address
+ *  Tests a MAC address to ensure it is a valid Individual Address.
  **/
 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
 {
@@ -2252,16 +2253,13 @@ s32 ixgbe_validate_mac_addr(u8 *mac_addr)
 
        /* Make sure it is not a multicast address */
        if (IXGBE_IS_MULTICAST(mac_addr)) {
-               DEBUGOUT("MAC address is multicast\n");
                status = IXGBE_ERR_INVALID_MAC_ADDR;
        /* Not a broadcast address */
        } else if (IXGBE_IS_BROADCAST(mac_addr)) {
-               DEBUGOUT("MAC address is broadcast\n");
                status = IXGBE_ERR_INVALID_MAC_ADDR;
        /* Reject the zero address */
        } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
                   mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
-               DEBUGOUT("MAC address is all zeros\n");
                status = IXGBE_ERR_INVALID_MAC_ADDR;
        }
        return status;
@@ -3572,6 +3570,7 @@ u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
        case ixgbe_mac_X540:
        case ixgbe_mac_X550:
        case ixgbe_mac_X550EM_x:
+       case ixgbe_mac_X550EM_a:
                pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
                max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
                break;
@@ -4067,7 +4066,7 @@ s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
        }
 
        if (link_up_wait_to_complete) {
-               for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
+               for (i = 0; i < hw->mac.max_link_up_time; i++) {
                        if (links_reg & IXGBE_LINKS_UP) {
                                *link_up = true;
                                break;
@@ -4882,7 +4881,7 @@ bool ixgbe_mng_present(struct ixgbe_hw *hw)
        if (hw->mac.type < ixgbe_mac_82599EB)
                return false;
 
-       fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
+       fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
        fwsm &= IXGBE_FWSM_MODE_MASK;
        return fwsm == IXGBE_FWSM_FW_MODE_PT;
 }
@@ -4897,7 +4896,7 @@ bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
 {
        u32 fwsm, manc, factps;
 
-       fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
+       fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw));
        if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
                return false;
 
@@ -4906,7 +4905,7 @@ bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
                return false;
 
        if (hw->mac.type <= ixgbe_mac_X540) {
-               factps = IXGBE_READ_REG(hw, IXGBE_FACTPS);
+               factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw));
                if (factps & IXGBE_FACTPS_MNGCG)
                        return false;
        }
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