/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2018
+ * Copyright(c) 2001-2020 Intel Corporation
*/
#include "ixgbe_api.h"
STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
-STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
+STATIC void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
-STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
+STATIC void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
*/
STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
{
- s32 status;
-
- status = ixgbe_clock_in_i2c_byte(hw, byte);
- if (status)
- return status;
+ ixgbe_clock_in_i2c_byte(hw, byte);
/* ACK */
return ixgbe_clock_out_i2c_bit(hw, false);
}
if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
goto fail;
/* Get csum */
- if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
- goto fail;
+ ixgbe_clock_in_i2c_byte(hw, &csum_byte);
/* NACK */
if (ixgbe_clock_out_i2c_bit(hw, false))
goto fail;
ixgbe_i2c_bus_clear(hw);
if (lock)
hw->mac.ops.release_swfw_sync(hw, swfw_mask);
- retry++;
if (retry < max_retry)
DEBUGOUT("I2C byte read combined error - Retrying.\n");
else
DEBUGOUT("I2C byte read combined error.\n");
- } while (retry < max_retry);
+ retry++;
+ } while (retry <= max_retry);
return IXGBE_ERR_I2C;
}
ixgbe_i2c_bus_clear(hw);
if (lock)
hw->mac.ops.release_swfw_sync(hw, swfw_mask);
- retry++;
if (retry < max_retry)
DEBUGOUT("I2C byte write combined error - Retrying.\n");
else
DEBUGOUT("I2C byte write combined error.\n");
- } while (retry < max_retry);
+ retry++;
+ } while (retry <= max_retry);
return IXGBE_ERR_I2C;
}
/**
- * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
- * @hw: pointer to the hardware structure
+ * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
+ * @hw: pointer to the hardware structure
*
- * Initialize the function pointers.
+ * Initialize the function pointers.
**/
s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
{
}
/**
- * ixgbe_identify_phy_generic - Get physical layer module
- * @hw: pointer to hardware structure
+ * ixgbe_identify_phy_generic - Get physical layer module
+ * @hw: pointer to hardware structure
*
- * Determines the physical layer module found on the current adapter.
+ * Determines the physical layer module found on the current adapter.
**/
s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
{
}
/**
- * ixgbe_validate_phy_addr - Determines phy address is valid
- * @hw: pointer to hardware structure
- * @phy_addr: PHY address
+ * ixgbe_validate_phy_addr - Determines phy address is valid
+ * @hw: pointer to hardware structure
+ * @phy_addr: PHY address
*
**/
bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
}
/**
- * ixgbe_get_phy_id - Get the phy type
- * @hw: pointer to hardware structure
+ * ixgbe_get_phy_id - Get the phy type
+ * @hw: pointer to hardware structure
*
**/
s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
}
/**
- * ixgbe_get_phy_type_from_id - Get the phy type
- * @phy_id: PHY ID information
+ * ixgbe_get_phy_type_from_id - Get the phy type
+ * @phy_id: PHY ID information
*
**/
enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
}
/**
- * ixgbe_reset_phy_generic - Performs a PHY reset
- * @hw: pointer to hardware structure
+ * ixgbe_reset_phy_generic - Performs a PHY reset
+ * @hw: pointer to hardware structure
**/
s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
{
}
/**
- * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
- * the SWFW lock
- * @hw: pointer to hardware structure
- * @reg_addr: 32 bit address of PHY register to read
- * @device_type: 5 bit device type
- * @phy_data: Pointer to read data from PHY register
+ * ixgbe_restart_auto_neg - Restart auto negotiation on the PHY
+ * @hw: pointer to hardware structure
+ **/
+void ixgbe_restart_auto_neg(struct ixgbe_hw *hw)
+{
+ u16 autoneg_reg;
+
+ /* Check if PHY reset is blocked by MNG FW */
+ if (ixgbe_check_reset_blocked(hw))
+ return;
+
+ /* Restart PHY auto-negotiation. */
+ hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
+ IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
+ autoneg_reg |= IXGBE_MII_RESTART;
+ hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
+ IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
+}
+
+/**
+ * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
+ * the SWFW lock
+ * @hw: pointer to hardware structure
+ * @reg_addr: 32 bit address of PHY register to read
+ * @device_type: 5 bit device type
+ * @phy_data: Pointer to read data from PHY register
**/
s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
u16 *phy_data)
}
/**
- * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
- * using the SWFW lock - this function is needed in most cases
- * @hw: pointer to hardware structure
- * @reg_addr: 32 bit address of PHY register to read
- * @device_type: 5 bit device type
- * @phy_data: Pointer to read data from PHY register
+ * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
+ * using the SWFW lock - this function is needed in most cases
+ * @hw: pointer to hardware structure
+ * @reg_addr: 32 bit address of PHY register to read
+ * @device_type: 5 bit device type
+ * @phy_data: Pointer to read data from PHY register
**/
s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
u32 device_type, u16 *phy_data)
}
/**
- * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
- * without SWFW lock
- * @hw: pointer to hardware structure
- * @reg_addr: 32 bit PHY register to write
- * @device_type: 5 bit device type
- * @phy_data: Data to write to the PHY register
+ * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
+ * without SWFW lock
+ * @hw: pointer to hardware structure
+ * @reg_addr: 32 bit PHY register to write
+ * @device_type: 5 bit device type
+ * @phy_data: Data to write to the PHY register
**/
s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
u32 device_type, u16 phy_data)
}
/**
- * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
- * using SWFW lock- this function is needed in most cases
- * @hw: pointer to hardware structure
- * @reg_addr: 32 bit PHY register to write
- * @device_type: 5 bit device type
- * @phy_data: Data to write to the PHY register
+ * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
+ * using SWFW lock- this function is needed in most cases
+ * @hw: pointer to hardware structure
+ * @reg_addr: 32 bit PHY register to write
+ * @device_type: 5 bit device type
+ * @phy_data: Data to write to the PHY register
**/
s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
u32 device_type, u16 phy_data)
}
/**
- * ixgbe_setup_phy_link_generic - Set and restart auto-neg
- * @hw: pointer to hardware structure
+ * ixgbe_setup_phy_link_generic - Set and restart auto-neg
+ * @hw: pointer to hardware structure
*
- * Restart auto-negotiation and PHY and waits for completion.
+ * Restart auto-negotiation and PHY and waits for completion.
**/
s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
{
IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
autoneg_reg);
- /* Blocked by MNG FW so don't reset PHY */
- if (ixgbe_check_reset_blocked(hw))
- return status;
-
- /* Restart PHY auto-negotiation. */
- hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
-
- autoneg_reg |= IXGBE_MII_RESTART;
-
- hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
-
+ ixgbe_restart_auto_neg(hw);
return status;
}
/**
- * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
- * @hw: pointer to hardware structure
- * @speed: new link speed
- * @autoneg_wait_to_complete: unused
+ * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
+ * @hw: pointer to hardware structure
+ * @speed: new link speed
+ * @autoneg_wait_to_complete: unused
**/
s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
ixgbe_link_speed speed,
hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
switch (hw->mac.type) {
- case ixgbe_mac_X550:
- hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
- hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
- break;
case ixgbe_mac_X550EM_x:
case ixgbe_mac_X550EM_a:
hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
}
/**
- * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
- * @hw: pointer to hardware structure
- * @speed: pointer to link speed
- * @autoneg: boolean auto-negotiation value
+ * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
+ * @hw: pointer to hardware structure
+ * @speed: pointer to link speed
+ * @autoneg: boolean auto-negotiation value
**/
s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
ixgbe_link_speed *speed,
}
/**
- * ixgbe_check_phy_link_tnx - Determine link and speed status
- * @hw: pointer to hardware structure
- * @speed: current link speed
- * @link_up: true is link is up, false otherwise
+ * ixgbe_check_phy_link_tnx - Determine link and speed status
+ * @hw: pointer to hardware structure
+ * @speed: current link speed
+ * @link_up: true is link is up, false otherwise
*
- * Reads the VS1 register to determine if link is up and the current speed for
- * the PHY.
+ * Reads the VS1 register to determine if link is up and the current speed for
+ * the PHY.
**/
s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
bool *link_up)
autoneg_reg);
}
- /* Blocked by MNG FW so don't reset PHY */
- if (ixgbe_check_reset_blocked(hw))
- return status;
-
- /* Restart PHY auto-negotiation. */
- hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
-
- autoneg_reg |= IXGBE_MII_RESTART;
-
- hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
- IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
-
+ ixgbe_restart_auto_neg(hw);
return status;
}
/**
- * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
- * @hw: pointer to hardware structure
- * @firmware_version: pointer to the PHY Firmware Version
+ * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
+ * @hw: pointer to hardware structure
+ * @firmware_version: pointer to the PHY Firmware Version
**/
s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
u16 *firmware_version)
}
/**
- * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
- * @hw: pointer to hardware structure
- * @firmware_version: pointer to the PHY Firmware Version
+ * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
+ * @hw: pointer to hardware structure
+ * @firmware_version: pointer to the PHY Firmware Version
**/
s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
u16 *firmware_version)
}
/**
- * ixgbe_reset_phy_nl - Performs a PHY reset
- * @hw: pointer to hardware structure
+ * ixgbe_reset_phy_nl - Performs a PHY reset
+ * @hw: pointer to hardware structure
**/
s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
{
}
/**
- * ixgbe_identify_module_generic - Identifies module type
- * @hw: pointer to hardware structure
+ * ixgbe_identify_module_generic - Identifies module type
+ * @hw: pointer to hardware structure
*
- * Determines HW type and calls appropriate function.
+ * Determines HW type and calls appropriate function.
**/
s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
{
}
/**
- * ixgbe_identify_sfp_module_generic - Identifies SFP modules
- * @hw: pointer to hardware structure
+ * ixgbe_identify_sfp_module_generic - Identifies SFP modules
+ * @hw: pointer to hardware structure
*
- * Searches for and identifies the SFP module and assigns appropriate PHY type.
+ * Searches for and identifies the SFP module and assigns appropriate PHY type.
**/
s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
{
else
hw->phy.sfp_type =
ixgbe_sfp_type_1g_lx_core1;
+ } else if (comp_codes_1g & IXGBE_SFF_1GBASELHA_CAPABLE) {
+ if (hw->bus.lan_id == 0)
+ hw->phy.sfp_type =
+ ixgbe_sfp_type_1g_lha_core0;
+ else
+ hw->phy.sfp_type =
+ ixgbe_sfp_type_1g_lha_core1;
} else {
hw->phy.sfp_type = ixgbe_sfp_type_unknown;
}
if (comp_codes_10g == 0 &&
!(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
+ hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core0 ||
+ hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core1 ||
hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
!(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
+ hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core0 ||
+ hw->phy.sfp_type == ixgbe_sfp_type_1g_lha_core1 ||
hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
}
/**
- * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
- * @hw: pointer to hardware structure
+ * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
+ * @hw: pointer to hardware structure
*
- * Determines physical layer capabilities of the current SFP.
+ * Determines physical layer capabilities of the current SFP.
*/
u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
{
}
/**
- * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
- * @hw: pointer to hardware structure
+ * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
+ * @hw: pointer to hardware structure
*
- * Searches for and identifies the QSFP module and assigns appropriate PHY type
+ * Searches for and identifies the QSFP module and assigns appropriate PHY type
**/
s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
{
}
/**
- * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
- * @hw: pointer to hardware structure
- * @list_offset: offset to the SFP ID list
- * @data_offset: offset to the SFP data block
+ * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
+ * @hw: pointer to hardware structure
+ * @list_offset: offset to the SFP ID list
+ * @data_offset: offset to the SFP data block
*
- * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
- * so it returns the offsets to the phy init sequence block.
+ * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
+ * so it returns the offsets to the phy init sequence block.
**/
s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
u16 *list_offset,
*/
if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
+ sfp_type == ixgbe_sfp_type_1g_lha_core0 ||
sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
sfp_type == ixgbe_sfp_type_1g_sx_core0)
sfp_type = ixgbe_sfp_type_srlr_core0;
else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
+ sfp_type == ixgbe_sfp_type_1g_lha_core1 ||
sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
sfp_type == ixgbe_sfp_type_1g_sx_core1)
sfp_type = ixgbe_sfp_type_srlr_core1;
}
/**
- * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
- * @hw: pointer to hardware structure
- * @byte_offset: EEPROM byte offset to read
- * @eeprom_data: value read
+ * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
+ * @hw: pointer to hardware structure
+ * @byte_offset: EEPROM byte offset to read
+ * @eeprom_data: value read
*
- * Performs byte read operation to SFP module's EEPROM over I2C interface.
+ * Performs byte read operation to SFP module's EEPROM over I2C interface.
**/
s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
u8 *eeprom_data)
}
/**
- * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
- * @hw: pointer to hardware structure
- * @byte_offset: byte offset at address 0xA2
- * @sff8472_data: value read
+ * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
+ * @hw: pointer to hardware structure
+ * @byte_offset: byte offset at address 0xA2
+ * @sff8472_data: value read
*
- * Performs byte read operation to SFP module's SFF-8472 data over I2C
+ * Performs byte read operation to SFP module's SFF-8472 data over I2C
**/
STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
u8 *sff8472_data)
}
/**
- * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
- * @hw: pointer to hardware structure
- * @byte_offset: EEPROM byte offset to write
- * @eeprom_data: value to write
+ * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
+ * @hw: pointer to hardware structure
+ * @byte_offset: EEPROM byte offset to write
+ * @eeprom_data: value to write
*
- * Performs byte write operation to SFP module's EEPROM over I2C interface.
+ * Performs byte write operation to SFP module's EEPROM over I2C interface.
**/
s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
u8 eeprom_data)
}
/**
- * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
- * @hw: pointer to hardware structure
- * @byte_offset: byte offset to read
- * @dev_addr: address to read from
- * @data: value read
- * @lock: true if to take and release semaphore
+ * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
+ * @hw: pointer to hardware structure
+ * @byte_offset: byte offset to read
+ * @dev_addr: address to read from
+ * @data: value read
+ * @lock: true if to take and release semaphore
*
- * Performs byte read operation to SFP module's EEPROM over I2C interface at
- * a specified device address.
+ * Performs byte read operation to SFP module's EEPROM over I2C interface at
+ * a specified device address.
**/
STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 *data, bool lock)
if (status != IXGBE_SUCCESS)
goto fail;
- status = ixgbe_clock_in_i2c_byte(hw, data);
- if (status != IXGBE_SUCCESS)
- goto fail;
+ ixgbe_clock_in_i2c_byte(hw, data);
status = ixgbe_clock_out_i2c_bit(hw, nack);
if (status != IXGBE_SUCCESS)
hw->mac.ops.release_swfw_sync(hw, swfw_mask);
msec_delay(100);
}
- retry++;
if (retry < max_retry)
DEBUGOUT("I2C byte read error - Retrying.\n");
else
DEBUGOUT("I2C byte read error.\n");
-
- } while (retry < max_retry);
+ retry++;
+ } while (retry <= max_retry);
return status;
}
/**
- * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
- * @hw: pointer to hardware structure
- * @byte_offset: byte offset to read
- * @dev_addr: address to read from
- * @data: value read
+ * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
+ * @hw: pointer to hardware structure
+ * @byte_offset: byte offset to read
+ * @dev_addr: address to read from
+ * @data: value read
*
- * Performs byte read operation to SFP module's EEPROM over I2C interface at
- * a specified device address.
+ * Performs byte read operation to SFP module's EEPROM over I2C interface at
+ * a specified device address.
**/
s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 *data)
}
/**
- * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
- * @hw: pointer to hardware structure
- * @byte_offset: byte offset to read
- * @dev_addr: address to read from
- * @data: value read
+ * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
+ * @hw: pointer to hardware structure
+ * @byte_offset: byte offset to read
+ * @dev_addr: address to read from
+ * @data: value read
*
- * Performs byte read operation to SFP module's EEPROM over I2C interface at
- * a specified device address.
+ * Performs byte read operation to SFP module's EEPROM over I2C interface at
+ * a specified device address.
**/
s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 *data)
}
/**
- * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
- * @hw: pointer to hardware structure
- * @byte_offset: byte offset to write
- * @dev_addr: address to write to
- * @data: value to write
- * @lock: true if to take and release semaphore
+ * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
+ * @hw: pointer to hardware structure
+ * @byte_offset: byte offset to write
+ * @dev_addr: address to write to
+ * @data: value to write
+ * @lock: true if to take and release semaphore
*
- * Performs byte write operation to SFP module's EEPROM over I2C interface at
- * a specified device address.
+ * Performs byte write operation to SFP module's EEPROM over I2C interface at
+ * a specified device address.
**/
STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 data, bool lock)
fail:
ixgbe_i2c_bus_clear(hw);
- retry++;
if (retry < max_retry)
DEBUGOUT("I2C byte write error - Retrying.\n");
else
DEBUGOUT("I2C byte write error.\n");
- } while (retry < max_retry);
+ retry++;
+ } while (retry <= max_retry);
if (lock)
hw->mac.ops.release_swfw_sync(hw, swfw_mask);
}
/**
- * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
- * @hw: pointer to hardware structure
- * @byte_offset: byte offset to write
- * @dev_addr: address to write to
- * @data: value to write
+ * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
+ * @hw: pointer to hardware structure
+ * @byte_offset: byte offset to write
+ * @dev_addr: address to write to
+ * @data: value to write
*
- * Performs byte write operation to SFP module's EEPROM over I2C interface at
- * a specified device address.
+ * Performs byte write operation to SFP module's EEPROM over I2C interface at
+ * a specified device address.
**/
s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 data)
}
/**
- * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
- * @hw: pointer to hardware structure
- * @byte_offset: byte offset to write
- * @dev_addr: address to write to
- * @data: value to write
+ * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
+ * @hw: pointer to hardware structure
+ * @byte_offset: byte offset to write
+ * @dev_addr: address to write to
+ * @data: value to write
*
- * Performs byte write operation to SFP module's EEPROM over I2C interface at
- * a specified device address.
+ * Performs byte write operation to SFP module's EEPROM over I2C interface at
+ * a specified device address.
**/
s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 data)
}
/**
- * ixgbe_i2c_start - Sets I2C start condition
- * @hw: pointer to hardware structure
+ * ixgbe_i2c_start - Sets I2C start condition
+ * @hw: pointer to hardware structure
*
- * Sets I2C start condition (High -> Low on SDA while SCL is High)
- * Set bit-bang mode on X550 hardware.
+ * Sets I2C start condition (High -> Low on SDA while SCL is High)
+ * Set bit-bang mode on X550 hardware.
**/
STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
{
}
/**
- * ixgbe_i2c_stop - Sets I2C stop condition
- * @hw: pointer to hardware structure
+ * ixgbe_i2c_stop - Sets I2C stop condition
+ * @hw: pointer to hardware structure
*
- * Sets I2C stop condition (Low -> High on SDA while SCL is High)
- * Disables bit-bang mode and negates data output enable on X550
- * hardware.
+ * Sets I2C stop condition (Low -> High on SDA while SCL is High)
+ * Disables bit-bang mode and negates data output enable on X550
+ * hardware.
**/
STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
{
}
/**
- * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
- * @hw: pointer to hardware structure
- * @data: data byte to clock in
+ * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
+ * @hw: pointer to hardware structure
+ * @data: data byte to clock in
*
- * Clocks in one byte data via I2C data/clock
+ * Clocks in one byte data via I2C data/clock
**/
-STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
+STATIC void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
{
s32 i;
bool bit = 0;
ixgbe_clock_in_i2c_bit(hw, &bit);
*data |= bit << i;
}
-
- return IXGBE_SUCCESS;
}
/**
- * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
- * @hw: pointer to hardware structure
- * @data: data byte clocked out
+ * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
+ * @hw: pointer to hardware structure
+ * @data: data byte clocked out
*
- * Clocks out one byte data via I2C data/clock
+ * Clocks out one byte data via I2C data/clock
**/
STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
{
}
/**
- * ixgbe_get_i2c_ack - Polls for I2C ACK
- * @hw: pointer to hardware structure
+ * ixgbe_get_i2c_ack - Polls for I2C ACK
+ * @hw: pointer to hardware structure
*
- * Clocks in/out one bit via I2C data/clock
+ * Clocks in/out one bit via I2C data/clock
**/
STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
{
}
/**
- * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
- * @hw: pointer to hardware structure
- * @data: read data value
+ * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
+ * @hw: pointer to hardware structure
+ * @data: read data value
*
- * Clocks in one bit via I2C data/clock
+ * Clocks in one bit via I2C data/clock
**/
-STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
+STATIC void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
{
u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
/* Minimum low period of clock is 4.7 us */
usec_delay(IXGBE_I2C_T_LOW);
-
- return IXGBE_SUCCESS;
}
/**
- * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
- * @hw: pointer to hardware structure
- * @data: data value to write
+ * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
+ * @hw: pointer to hardware structure
+ * @data: data value to write
*
- * Clocks out one bit via I2C data/clock
+ * Clocks out one bit via I2C data/clock
**/
STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
{
}
/**
- * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
- * @hw: pointer to hardware structure
- * @i2cctl: Current value of I2CCTL register
+ * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
+ * @hw: pointer to hardware structure
+ * @i2cctl: Current value of I2CCTL register
*
- * Raises the I2C clock line '0'->'1'
- * Negates the I2C clock output enable on X550 hardware.
+ * Raises the I2C clock line '0'->'1'
+ * Negates the I2C clock output enable on X550 hardware.
**/
STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
{
}
/**
- * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
- * @hw: pointer to hardware structure
- * @i2cctl: Current value of I2CCTL register
+ * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
+ * @hw: pointer to hardware structure
+ * @i2cctl: Current value of I2CCTL register
*
- * Lowers the I2C clock line '1'->'0'
- * Asserts the I2C clock output enable on X550 hardware.
+ * Lowers the I2C clock line '1'->'0'
+ * Asserts the I2C clock output enable on X550 hardware.
**/
STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
{
}
/**
- * ixgbe_set_i2c_data - Sets the I2C data bit
- * @hw: pointer to hardware structure
- * @i2cctl: Current value of I2CCTL register
- * @data: I2C data value (0 or 1) to set
+ * ixgbe_set_i2c_data - Sets the I2C data bit
+ * @hw: pointer to hardware structure
+ * @i2cctl: Current value of I2CCTL register
+ * @data: I2C data value (0 or 1) to set
*
- * Sets the I2C data bit
- * Asserts the I2C data output enable on X550 hardware.
+ * Sets the I2C data bit
+ * Asserts the I2C data output enable on X550 hardware.
**/
STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
{
}
/**
- * ixgbe_get_i2c_data - Reads the I2C SDA data bit
- * @hw: pointer to hardware structure
- * @i2cctl: Current value of I2CCTL register
+ * ixgbe_get_i2c_data - Reads the I2C SDA data bit
+ * @hw: pointer to hardware structure
+ * @i2cctl: Current value of I2CCTL register
*
- * Returns the I2C data bit value
- * Negates the I2C data output enable on X550 hardware.
+ * Returns the I2C data bit value
+ * Negates the I2C data output enable on X550 hardware.
**/
STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
{
u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
bool data;
- UNREFERENCED_1PARAMETER(hw);
DEBUGFUNC("ixgbe_get_i2c_data");
}
/**
- * ixgbe_i2c_bus_clear - Clears the I2C bus
- * @hw: pointer to hardware structure
+ * ixgbe_i2c_bus_clear - Clears the I2C bus
+ * @hw: pointer to hardware structure
*
- * Clears the I2C bus by sending nine clock pulses.
- * Used when data line is stuck low.
+ * Clears the I2C bus by sending nine clock pulses.
+ * Used when data line is stuck low.
**/
void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
{
}
/**
- * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
- * @hw: pointer to hardware structure
+ * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
+ * @hw: pointer to hardware structure
*
- * Checks if the LASI temp alarm status was triggered due to overtemp
+ * Checks if the LASI temp alarm status was triggered due to overtemp
**/
s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
{
git.droids-corp.org / dpdk.git / blobdiff