net/ixgbe: fix VF VLAN insert API

[dpdk.git] / drivers / net / ixgbe / base / ixgbe_type.h

diff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h
index 262f656..4982e03 100644 (file)
--- a/drivers/net/ixgbe/base/ixgbe_type.h
+++ b/drivers/net/ixgbe/base/ixgbe_type.h
@@ -565,6 +565,13 @@ struct ixgbe_thermal_sensor_data {
 #define IXGBE_PROXYFC  0x05F64 /* Proxying Filter Control Register */
 #define IXGBE_VXLANCTRL        0x0000507C /* Rx filter VXLAN UDPPORT Register */
 
+/* masks for accessing VXLAN and GENEVE UDP ports */
+#define IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK     0x0000ffff /* VXLAN port */
+#define IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK    0xffff0000 /* GENEVE port */
+#define IXGBE_VXLANCTRL_ALL_UDPPORT_MASK       0xffffffff /* GENEVE/VXLAN */
+
+#define IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT   16
+
 #define IXGBE_FHFT(_n) (0x09000 + ((_n) * 0x100)) /* Flex host filter table */
 /* Ext Flexible Host Filter Table */
 #define IXGBE_FHFT_EXT(_n)     (0x09800 + ((_n) * 0x100))
@@ -2206,6 +2213,7 @@ enum {
 #define IXGBE_LINKS_SPEED_10G_82599    0x30000000
 #define IXGBE_LINKS_SPEED_1G_82599     0x20000000
 #define IXGBE_LINKS_SPEED_100_82599    0x10000000
+#define IXGBE_LINKS_SPEED_10_X550EM_A  0x00000000
 #define IXGBE_LINK_UP_TIME             90 /* 9.0 Seconds */
 #define IXGBE_AUTO_NEG_TIME            45 /* 4.5 Seconds */
 
@@ -2785,6 +2793,7 @@ enum {
 #define IXGBE_RXDADV_PKTTYPE_UDP       0x00000200 /* UDP hdr present */
 #define IXGBE_RXDADV_PKTTYPE_SCTP      0x00000400 /* SCTP hdr present */
 #define IXGBE_RXDADV_PKTTYPE_NFS       0x00000800 /* NFS hdr present */
+#define IXGBE_RXDADV_PKTTYPE_GENEVE    0x00000800 /* GENEVE hdr present */
 #define IXGBE_RXDADV_PKTTYPE_VXLAN     0x00000800 /* VXLAN hdr present */
 #define IXGBE_RXDADV_PKTTYPE_TUNNEL    0x00010000 /* Tunnel type */
 #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */
@@ -3310,7 +3319,7 @@ typedef u32 ixgbe_autoneg_advertised;
 /* Link speed */
 typedef u32 ixgbe_link_speed;
 #define IXGBE_LINK_SPEED_UNKNOWN       0
-#define IXGBE_LINK_SPEED_10_FULL       0x0004
+#define IXGBE_LINK_SPEED_10_FULL       0x0002
 #define IXGBE_LINK_SPEED_100_FULL      0x0008
 #define IXGBE_LINK_SPEED_1GB_FULL      0x0020
 #define IXGBE_LINK_SPEED_2_5GB_FULL    0x0400
@@ -3845,6 +3854,7 @@ struct ixgbe_mac_operations {
        void (*init_swfw_sync)(struct ixgbe_hw *);
        s32 (*prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *);
        s32 (*prot_autoc_write)(struct ixgbe_hw *, u32, bool);
+       s32 (*negotiate_api_version)(struct ixgbe_hw *hw, int api);
 
        /* Link */
        void (*disable_tx_laser)(struct ixgbe_hw *);
@@ -3889,6 +3899,7 @@ struct ixgbe_mac_operations {
        void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
        void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
        s32 (*update_xcast_mode)(struct ixgbe_hw *, int);
+       s32 (*set_rlpml)(struct ixgbe_hw *, u16);
 
        /* Flow Control */
        s32 (*fc_enable)(struct ixgbe_hw *);
@@ -4153,9 +4164,25 @@ struct ixgbe_hw {
 #define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P) ? 0x8638 : 0x4638)
 #define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P)        ((P) ? 0x8B00 : 0x4B00)
 #define IXGBE_KRM_PMD_DFX_BURNIN(P)    ((P) ? 0x8E00 : 0x4E00)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20(P) ((P) ? 0x9054 : 0x5054)
 #define IXGBE_KRM_TX_COEFF_CTRL_1(P)   ((P) ? 0x9520 : 0x5520)
 #define IXGBE_KRM_RX_ANA_CTL(P)                ((P) ? 0x9A00 : 0x5A00)
 
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA         ~(0x3 << 20)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR         (1u << 20)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_LR         (0x2 << 20)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN           (1u << 25)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN            (1u << 26)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN              (1u << 27)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10M          ~(0x7 << 28)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_100M         (1u << 28)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G           (0x2 << 28)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G          (0x3 << 28)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN           (0x4 << 28)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_2_5G         (0x7 << 28)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK         (0x7 << 28)
+#define IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART      (1u << 31)
+
 #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B           (1 << 9)
 #define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS         (1 << 11)
 
@@ -4225,6 +4252,11 @@ struct ixgbe_hw {
 #define IXGBE_NW_MNG_IF_SEL_MDIO_ACT   (1u << 1)
 #define IXGBE_NW_MNG_IF_SEL_MDIO_IF_MODE       (1u << 2)
 #define IXGBE_NW_MNG_IF_SEL_EN_SHARED_MDIO     (1u << 13)
+#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10M      (1u << 17)
+#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_100M     (1u << 18)
+#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_1G       (1u << 19)
+#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G     (1u << 20)
+#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10G      (1u << 21)
 #define IXGBE_NW_MNG_IF_SEL_ENABLE_10_100M (1 << 23)
 #define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE (1 << 24)
 #define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT 3