ixgbe/base: abstract out link read/write

[dpdk.git] / drivers / net / ixgbe / base / ixgbe_x540.c

diff --git a/drivers/net/ixgbe/base/ixgbe_x540.c b/drivers/net/ixgbe/base/ixgbe_x540.c
index 6e8835d..9ade1b5 100644 (file)
--- a/drivers/net/ixgbe/base/ixgbe_x540.c
+++ b/drivers/net/ixgbe/base/ixgbe_x540.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 
-Copyright (c) 2001-2014, Intel Corporation
+Copyright (c) 2001-2015, Intel Corporation
 All rights reserved.
 
 Redistribution and use in source and binary forms, with or without
@@ -81,8 +81,7 @@ s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
        /* PHY */
        phy->ops.init = ixgbe_init_phy_ops_generic;
        phy->ops.reset = NULL;
-       if (!ixgbe_mng_present(hw))
-               phy->ops.set_phy_power = ixgbe_set_copper_phy_power;
+       phy->ops.set_phy_power = ixgbe_set_copper_phy_power;
 
        /* MAC */
        mac->ops.reset_hw = ixgbe_reset_hw_X540;
@@ -137,8 +136,8 @@ s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
         * ARC supported; valid only if manageability features are
         * enabled.
         */
-       mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
-                                  IXGBE_FWSM_MODE_MASK) ? true : false;
+       mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw))
+                                    & IXGBE_FWSM_MODE_MASK);
 
        hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
 
@@ -355,7 +354,7 @@ s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
                eeprom->semaphore_delay = 10;
                eeprom->type = ixgbe_flash;
 
-               eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+               eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
                eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
                                    IXGBE_EEC_SIZE_SHIFT);
                eeprom->word_size = 1 << (eeprom_size +
@@ -680,8 +679,8 @@ s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
                goto out;
        }
 
-       flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
-       IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
+       flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)) | IXGBE_EEC_FLUP;
+       IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup);
 
        status = ixgbe_poll_flash_update_done_X540(hw);
        if (status == IXGBE_SUCCESS)
@@ -690,11 +689,11 @@ s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
                DEBUGOUT("Flash update time out\n");
 
        if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) {
-               flup = IXGBE_READ_REG(hw, IXGBE_EEC);
+               flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
 
                if (flup & IXGBE_EEC_SEC1VAL) {
                        flup |= IXGBE_EEC_FLUP;
-                       IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
+                       IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup);
                }
 
                status = ixgbe_poll_flash_update_done_X540(hw);
@@ -723,7 +722,7 @@ STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
        DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
 
        for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
-               reg = IXGBE_READ_REG(hw, IXGBE_EEC);
+               reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw));
                if (reg & IXGBE_EEC_FLUDONE) {
                        status = IXGBE_SUCCESS;
                        break;
@@ -738,26 +737,6 @@ STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
        return status;
 }
 
-/**
- * ixgbe_set_mux - Set mux for port 1 access with CS4227
- * @hw: pointer to hardware structure
- * @state: set mux if 1, clear if 0
- */
-STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
-{
-       u32 esdp;
-
-       if (!hw->bus.lan_id)
-               return;
-       esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
-       if (state)
-               esdp |= IXGBE_ESDP_SDP1;
-       else
-               esdp &= ~IXGBE_ESDP_SDP1;
-       IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
-       IXGBE_WRITE_FLUSH(hw);
-}
-
 /**
  *  ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
  *  @hw: pointer to hardware structure
@@ -794,14 +773,13 @@ s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
                if (ixgbe_get_swfw_sync_semaphore(hw))
                        return IXGBE_ERR_SWFW_SYNC;
 
-               swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
+               swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
                if (!(swfw_sync & (fwmask | swmask | hwmask))) {
                        swfw_sync |= swmask;
-                       IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
+                       IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw),
+                                       swfw_sync);
                        ixgbe_release_swfw_sync_semaphore(hw);
                        msec_delay(5);
-                       if (swi2c_mask)
-                               ixgbe_set_mux(hw, 1);
                        return IXGBE_SUCCESS;
                }
                /* Firmware currently using resource (fwmask), hardware
@@ -826,14 +804,12 @@ s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
         */
        if (ixgbe_get_swfw_sync_semaphore(hw))
                return IXGBE_ERR_SWFW_SYNC;
-       swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
+       swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
        if (swfw_sync & (fwmask | hwmask)) {
                swfw_sync |= swmask;
-               IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
+               IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
                ixgbe_release_swfw_sync_semaphore(hw);
                msec_delay(5);
-               if (swi2c_mask)
-                       ixgbe_set_mux(hw, 1);
                return IXGBE_SUCCESS;
        }
        /* If the resource is not released by other SW the SW can assume that
@@ -871,15 +847,13 @@ void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
 
        DEBUGFUNC("ixgbe_release_swfw_sync_X540");
 
-       if (mask & IXGBE_GSSR_I2C_MASK) {
+       if (mask & IXGBE_GSSR_I2C_MASK)
                swmask |= mask & IXGBE_GSSR_I2C_MASK;
-               ixgbe_set_mux(hw, 0);
-       }
        ixgbe_get_swfw_sync_semaphore(hw);
 
-       swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
+       swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
        swfw_sync &= ~swmask;
-       IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
+       IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync);
 
        ixgbe_release_swfw_sync_semaphore(hw);
        msec_delay(5);
@@ -906,7 +880,7 @@ STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
                 * If the SMBI bit is 0 when we read it, then the bit will be
                 * set and we have the semaphore
                 */
-               swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
+               swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
                if (!(swsm & IXGBE_SWSM_SMBI)) {
                        status = IXGBE_SUCCESS;
                        break;
@@ -917,7 +891,7 @@ STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
        /* Now get the semaphore between SW/FW through the REGSMP bit */
        if (status == IXGBE_SUCCESS) {
                for (i = 0; i < timeout; i++) {
-                       swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
+                       swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
                        if (!(swsm & IXGBE_SWFW_REGSMP))
                                break;
 
@@ -957,13 +931,13 @@ STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
 
        /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
 
-       swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
-       swsm &= ~IXGBE_SWSM_SMBI;
-       IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
-
-       swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
+       swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw));
        swsm &= ~IXGBE_SWFW_REGSMP;
-       IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
+       IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swsm);
+
+       swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw));
+       swsm &= ~IXGBE_SWSM_SMBI;
+       IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm);
 
        IXGBE_WRITE_FLUSH(hw);
 }
@@ -1036,5 +1010,3 @@ s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
 
        return IXGBE_SUCCESS;
 }
-
-