net/ixgbe: convert to new Rx offloads API
[dpdk.git] / drivers / net / ixgbe / ixgbe_ipsec.c
index 85305c6..29e4728 100644 (file)
@@ -2,7 +2,7 @@
  * Copyright(c) 2010-2017 Intel Corporation
  */
 
-#include <rte_ethdev.h>
+#include <rte_ethdev_driver.h>
 #include <rte_ethdev_pci.h>
 #include <rte_ip.h>
 #include <rte_jhash.h>
@@ -402,6 +402,12 @@ ixgbe_crypto_create_session(void *device,
        return 0;
 }
 
+static unsigned int
+ixgbe_crypto_session_get_size(__rte_unused void *device)
+{
+       return sizeof(struct ixgbe_crypto_session);
+}
+
 static int
 ixgbe_crypto_remove_session(void *device,
                struct rte_security_session *session)
@@ -592,13 +598,15 @@ ixgbe_crypto_enable_ipsec(struct rte_eth_dev *dev)
 {
        struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
        uint32_t reg;
+       uint64_t rx_offloads;
 
+       rx_offloads = dev->data->dev_conf.rxmode.offloads;
        /* sanity checks */
-       if (dev->data->dev_conf.rxmode.enable_lro) {
+       if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) {
                PMD_DRV_LOG(ERR, "RSC and IPsec not supported");
                return -1;
        }
-       if (!dev->data->dev_conf.rxmode.hw_strip_crc) {
+       if (!(rx_offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
                PMD_DRV_LOG(ERR, "HW CRC strip needs to be enabled for IPsec");
                return -1;
        }
@@ -618,7 +626,7 @@ ixgbe_crypto_enable_ipsec(struct rte_eth_dev *dev)
        reg |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
        IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg);
 
-       if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SECURITY) {
+       if (rx_offloads & DEV_RX_OFFLOAD_SECURITY) {
                IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, 0);
                reg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
                if (reg != 0) {
@@ -674,21 +682,44 @@ ixgbe_crypto_add_ingress_sa_from_flow(const void *sess,
 static struct rte_security_ops ixgbe_security_ops = {
        .session_create = ixgbe_crypto_create_session,
        .session_update = NULL,
+       .session_get_size = ixgbe_crypto_session_get_size,
        .session_stats_get = NULL,
        .session_destroy = ixgbe_crypto_remove_session,
        .set_pkt_metadata = ixgbe_crypto_update_mb,
        .capabilities_get = ixgbe_crypto_capabilities_get
 };
 
-struct rte_security_ctx *
+static int
+ixgbe_crypto_capable(struct rte_eth_dev *dev)
+{
+       struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+       uint32_t reg_i, reg, capable = 1;
+       /* test if rx crypto can be enabled and then write back initial value*/
+       reg_i = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
+       IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, 0);
+       reg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
+       if (reg != 0)
+               capable = 0;
+       IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, reg_i);
+       return capable;
+}
+
+int
 ixgbe_ipsec_ctx_create(struct rte_eth_dev *dev)
 {
-       struct rte_security_ctx *ctx = rte_malloc("rte_security_instances_ops",
-                                       sizeof(struct rte_security_ctx), 0);
-       if (ctx) {
-               ctx->device = (void *)dev;
-               ctx->ops = &ixgbe_security_ops;
-               ctx->sess_cnt = 0;
+       struct rte_security_ctx *ctx = NULL;
+
+       if (ixgbe_crypto_capable(dev)) {
+               ctx = rte_malloc("rte_security_instances_ops",
+                                sizeof(struct rte_security_ctx), 0);
+               if (ctx) {
+                       ctx->device = (void *)dev;
+                       ctx->ops = &ixgbe_security_ops;
+                       ctx->sess_cnt = 0;
+                       dev->security_ctx = ctx;
+               } else {
+                       return -ENOMEM;
+               }
        }
-       return ctx;
+       return 0;
 }