net/enetc: batch process clean Tx ring calls

[dpdk.git] / drivers / net / ixgbe / rte_pmd_ixgbe.c

diff --git a/drivers/net/ixgbe/rte_pmd_ixgbe.c b/drivers/net/ixgbe/rte_pmd_ixgbe.c
index 077afab..8bcaded 100644 (file)
--- a/drivers/net/ixgbe/rte_pmd_ixgbe.c
+++ b/drivers/net/ixgbe/rte_pmd_ixgbe.c
@@ -515,82 +515,20 @@ rte_pmd_ixgbe_set_vf_rate_limit(uint16_t port, uint16_t vf,
 int
 rte_pmd_ixgbe_macsec_enable(uint16_t port, uint8_t en, uint8_t rp)
 {
-       struct ixgbe_hw *hw;
        struct rte_eth_dev *dev;
-       uint32_t ctrl;
+       struct ixgbe_macsec_setting macsec_setting;
 
        RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
 
        dev = &rte_eth_devices[port];
 
-       if (!is_ixgbe_supported(dev))
-               return -ENOTSUP;
+       macsec_setting.offload_en = 1;
+       macsec_setting.encrypt_en = en;
+       macsec_setting.replayprotect_en = rp;
 
-       hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+       ixgbe_dev_macsec_setting_save(dev, &macsec_setting);
 
-       /* Stop the data paths */
-       if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
-               return -ENOTSUP;
-       /**
-        * Workaround:
-        * As no ixgbe_disable_sec_rx_path equivalent is
-        * implemented for tx in the base code, and we are
-        * not allowed to modify the base code in DPDK, so
-        * just call the hand-written one directly for now.
-        * The hardware support has been checked by
-        * ixgbe_disable_sec_rx_path().
-        */
-       ixgbe_disable_sec_tx_path_generic(hw);
-
-       /* Enable Ethernet CRC (required by MACsec offload) */
-       ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
-       ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
-       IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
-
-       /* Enable the TX and RX crypto engines */
-       ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
-       ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
-       IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
-
-       ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
-       ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
-       IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
-
-       ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
-       ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
-       ctrl |= 0x3;
-       IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
-
-       /* Enable SA lookup */
-       ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
-       ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
-       ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
-                    IXGBE_LSECTXCTRL_AUTH;
-       ctrl |= IXGBE_LSECTXCTRL_AISCI;
-       ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
-       ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
-       IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
-
-       ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
-       ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
-       ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
-       ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
-       if (rp)
-               ctrl |= IXGBE_LSECRXCTRL_RP;
-       else
-               ctrl &= ~IXGBE_LSECRXCTRL_RP;
-       IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
-
-       /* Start the data paths */
-       ixgbe_enable_sec_rx_path(hw);
-       /**
-        * Workaround:
-        * As no ixgbe_enable_sec_rx_path equivalent is
-        * implemented for tx in the base code, and we are
-        * not allowed to modify the base code in DPDK, so
-        * just call the hand-written one directly for now.
-        */
-       ixgbe_enable_sec_tx_path_generic(hw);
+       ixgbe_dev_macsec_register_enable(dev, &macsec_setting);
 
        return 0;
 }
@@ -598,63 +536,15 @@ rte_pmd_ixgbe_macsec_enable(uint16_t port, uint8_t en, uint8_t rp)
 int
 rte_pmd_ixgbe_macsec_disable(uint16_t port)
 {
-       struct ixgbe_hw *hw;
        struct rte_eth_dev *dev;
-       uint32_t ctrl;
 
        RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
 
        dev = &rte_eth_devices[port];
 
-       if (!is_ixgbe_supported(dev))
-               return -ENOTSUP;
-
-       hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+       ixgbe_dev_macsec_setting_reset(dev);
 
-       /* Stop the data paths */
-       if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
-               return -ENOTSUP;
-       /**
-        * Workaround:
-        * As no ixgbe_disable_sec_rx_path equivalent is
-        * implemented for tx in the base code, and we are
-        * not allowed to modify the base code in DPDK, so
-        * just call the hand-written one directly for now.
-        * The hardware support has been checked by
-        * ixgbe_disable_sec_rx_path().
-        */
-       ixgbe_disable_sec_tx_path_generic(hw);
-
-       /* Disable the TX and RX crypto engines */
-       ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
-       ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
-       IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
-
-       ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
-       ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
-       IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
-
-       /* Disable SA lookup */
-       ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
-       ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
-       ctrl |= IXGBE_LSECTXCTRL_DISABLE;
-       IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
-
-       ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
-       ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
-       ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
-       IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
-
-       /* Start the data paths */
-       ixgbe_enable_sec_rx_path(hw);
-       /**
-        * Workaround:
-        * As no ixgbe_enable_sec_rx_path equivalent is
-        * implemented for tx in the base code, and we are
-        * not allowed to modify the base code in DPDK, so
-        * just call the hand-written one directly for now.
-        */
-       ixgbe_enable_sec_tx_path_generic(hw);
+       ixgbe_dev_macsec_register_disable(dev);
 
        return 0;
 }
@@ -882,7 +772,7 @@ rte_pmd_ixgbe_set_tc_bw_alloc(uint16_t port,
        return 0;
 }
 
-int __rte_experimental
+int
 rte_pmd_ixgbe_upd_fctrl_sbp(uint16_t port, int enable)
 {
        struct ixgbe_hw *hw;
@@ -1096,7 +986,7 @@ STATIC void rte_pmd_ixgbe_release_swfw(struct ixgbe_hw *hw, u32 mask)
        ixgbe_release_swfw_semaphore(hw, mask);
 }
 
-int __rte_experimental
+int
 rte_pmd_ixgbe_mdio_lock(uint16_t port)
 {
        struct ixgbe_hw *hw;
@@ -1123,7 +1013,7 @@ rte_pmd_ixgbe_mdio_lock(uint16_t port)
        return IXGBE_SUCCESS;
 }
 
-int __rte_experimental
+int
 rte_pmd_ixgbe_mdio_unlock(uint16_t port)
 {
        struct rte_eth_dev *dev;
@@ -1150,7 +1040,7 @@ rte_pmd_ixgbe_mdio_unlock(uint16_t port)
        return IXGBE_SUCCESS;
 }
 
-int __rte_experimental
+int
 rte_pmd_ixgbe_mdio_unlocked_read(uint16_t port, uint32_t reg_addr,
                                 uint32_t dev_type, uint16_t *phy_data)
 {
@@ -1197,7 +1087,7 @@ rte_pmd_ixgbe_mdio_unlocked_read(uint16_t port, uint32_t reg_addr,
        return 0;
 }
 
-int __rte_experimental
+int
 rte_pmd_ixgbe_mdio_unlocked_write(uint16_t port, uint32_t reg_addr,
                                  uint32_t dev_type, uint16_t phy_data)
 {