-/*
- * BSD LICENSE
- *
- * Copyright(c) 2017 Cavium, Inc.. All rights reserved.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Cavium, Inc. nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2017 Cavium, Inc
*/
#ifndef _LIO_STRUCT_H_
uint16_t reserved;
};
+/** Input Queue statistics. Each input queue has four stats fields. */
+struct lio_iq_stats {
+ uint64_t instr_posted; /**< Instructions posted to this queue. */
+ uint64_t instr_processed; /**< Instructions processed in this queue. */
+ uint64_t instr_dropped; /**< Instructions that could not be processed */
+ uint64_t bytes_sent; /**< Bytes sent through this queue. */
+ uint64_t tx_done; /**< Num of packets sent to network. */
+ uint64_t tx_iq_busy; /**< Num of times this iq was found to be full. */
+ uint64_t tx_dropped; /**< Num of pkts dropped due to xmitpath errors. */
+ uint64_t tx_tot_bytes; /**< Total count of bytes sent to network. */
+};
+
+/** Output Queue statistics. Each output queue has four stats fields. */
+struct lio_droq_stats {
+ /** Number of packets received in this queue. */
+ uint64_t pkts_received;
+
+ /** Bytes received by this queue. */
+ uint64_t bytes_received;
+
+ /** Packets dropped due to no memory available. */
+ uint64_t dropped_nomem;
+
+ /** Packets dropped due to large number of pkts to process. */
+ uint64_t dropped_toomany;
+
+ /** Number of packets sent to stack from this queue. */
+ uint64_t rx_pkts_received;
+
+ /** Number of Bytes sent to stack from this queue. */
+ uint64_t rx_bytes_received;
+
+ /** Num of Packets dropped due to receive path failures. */
+ uint64_t rx_dropped;
+
+ /** Num of vxlan packets received; */
+ uint64_t rx_vxlan;
+
+ /** Num of failures of rte_pktmbuf_alloc() */
+ uint64_t rx_alloc_failure;
+
+};
+
/** The Descriptor Ring Output Queue structure.
* This structure has all the information required to implement a
* DROQ.
rte_atomic64_t pkts_pending;
/** Number of descriptors in this ring. */
- uint32_t max_count;
+ uint32_t nb_desc;
/** The number of descriptors pending refill. */
uint32_t refill_count;
*/
void *pkts_sent_reg;
+ /** Statistics for this DROQ. */
+ struct lio_droq_stats stats;
+
/** DMA mapped address of the DROQ descriptor ring. */
size_t desc_ring_dma;
uint32_t status:8;
- /** Maximum no. of instructions in this queue. */
- uint32_t max_count;
+ /** Number of descriptors in this ring. */
+ uint32_t nb_desc;
/** Index in input ring where the driver should write the next packet */
uint32_t host_write_index;
/** Number of instructions pending to be posted to Octeon. */
uint32_t fill_cnt;
+ /** Statistics for this input queue. */
+ struct lio_iq_stats stats;
+
/** DMA mapped base address of the input descriptor ring. */
uint64_t base_addr_dma;
struct lio_sg_entry *sg;
};
+struct lio_rss_ctx {
+ uint16_t hash_key_size;
+ uint8_t hash_key[LIO_RSS_MAX_KEY_SZ];
+ /* Ideally a factor of number of queues */
+ uint8_t itable[LIO_RSS_MAX_TABLE_SZ];
+ uint8_t itable_size;
+ uint8_t ip;
+ uint8_t tcp_hash;
+ uint8_t ipv6;
+ uint8_t ipv6_tcp_hash;
+ uint8_t ipv6_ex;
+ uint8_t ipv6_tcp_ex_hash;
+ uint8_t hash_disable;
+};
+
struct lio_io_enable {
uint64_t iq;
uint64_t oq;
/** The state of this device */
rte_atomic64_t status;
+ uint8_t intf_open;
+
struct octeon_link_info linfo;
uint8_t *hw_addr;
uint8_t nb_rx_queues;
uint8_t nb_tx_queues;
uint8_t port_configured;
- uint8_t port_id;
+ struct lio_rss_ctx rss_state;
+ uint16_t port_id;
+ char firmware_version[LIO_FW_VERSION_LENGTH];
};
#endif /* _LIO_STRUCT_H_ */
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